Datasheet > CSSTV32852GKFREP

CSSTV32852GKFREP

更新时间： 2024-01-18 08:08:58

品牌	Logo	应用领域
德州仪器 - TI		输出元件输入元件
页数	文件大小	规格书
10页	374K
描述
24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS

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CSSTV32852GKFREP 数据手册

SN74SSTV32852-EP

24-BIT TO 48-BIT REGISTERED BUFFER

WITH SSTL_2 INPUTS AND OUTPUTS

www.ti.com

SCES700–OCTOBER 2007

FEATURES

•

Controlled Baseline

•

Supports SSTL_2 Data Inputs

–

One Assembly/Test Site, One Fabrication

Site

Outputs Meet SSTL_2 Class II Specifications

Differential Clock (CLK and CLK) Inputs

•

Extended Temperature Performance of –40°C

to 85°C

Supports LVCMOS Switching Levels on the

RESET Input

Enhanced Diminishing Manufacturing Sources

(DMS) Support

•

RESET Input Disables Differential Input

Receivers, Resets All Registers, and Forces

All Outputs Low

•

Enhanced Product-Change Notification

(1)

Qualification Pedigree

•

Pinout Optimizes DIMM PCB Layout

One Device Per DIMM Required

Member of the Texas Instruments Widebus™

Family

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

1-to-2 Outputs Support Stacked DDR DIMMs

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

•

ESD Protection Exceeds JESD 22

–

2000-V Human-Body Model (A114-A)

1000-V Charged-Device Model (C101)

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

DESCRIPTION/ORDERING INFORMATION

This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V V_CCoperation.

All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.

The SN74SSTV32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing of

CLK going high and CLK going low.

The device supports low-power standby operation. When RESET is low, the differential input receivers are

disabled, and undriven (floating) data, clock, and reference voltage (V_REF) inputs are allowed. In addition, when

RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must be

held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the

low state during power up.

ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE⁽²⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

SV852IEP

–40°C to 85°C

LFBGA – GKF Tape and reel

CSSTV32852GKFREP

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/packaging.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...10

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