CS44600
7.1.1 Increment (INCR) ................................................................................................ 48
7.1.2 Memory Address Pointer (MAPx) ....................................................................... 48
7.2 CS44600 I.D. and Revision Register (address 01h) (Read Only) ................................... 48
7.2.1 Chip I.D. (Chip_IDx) ............................................................................................ 48
7.2.2 Chip Revision (Rev_IDx) ..................................................................................... 48
7.3 Clock Configuration and Power Control (address 02h) ................................................... 49
7.3.1 Enable SYS_CLK Output (EN_SYS_CLK) ......................................................... 49
7.3.2 SYS_CLK Clock Divider Settings (SYS_CLK_DIV[1:0]) ..................................... 49
7.3.3 PWM Master Clock Divider Settings (PWM_MCLK_DIV[1:0]) ............................ 49
7.3.4 Power Down XTAL (PDN_XTAL) ........................................................................ 49
7.3.5 Power Down Output Mode (PDN_OUTPUT_MODE) ......................................... 50
7.3.6 Power Down (PDN) ............................................................................................. 50
7.4 PWM Channel Power Down Control (address 03h) ........................................................ 50
7.4.1 Power Down PWM Channels (PDN_PWMB3:PDN_PWMA1) ............................ 50
7.5 Misc. Configuration (address 04h) ................................................................................... 51
7.5.1 Digital Interface Format (DIFX) ........................................................................... 51
7.5.2 AM Frequency Hopping (AM_FREQ_HOP) ........................................................ 51
7.5.3 Freeze Controls (FREEZE) ................................................................................. 51
7.5.4 De-Emphasis Control (DEM[1:0]) ....................................................................... 52
7.6 Ramp Configuration (address 05h) ................................................................................. 52
7.6.1 Ramp-Up/Down Setting (RAMP[1:0]) ................................................................ 52
7.6.2 Ramp Speed (RAMP_SPD[1:0]) ......................................................................... 52
7.7 Volume Control Configuration (address 06h) .................................................................. 53
7.7.1 Single Volume Control (SNGVOL) ...................................................................... 53
7.7.2 Soft Ramp and Zero Cross Control (SZC[1:0]) ................................................... 53
7.7.3 Enable 50% Duty Cycle for Mute Condition (MUTE_50/50) ............................... 53
7.7.4 Soft Ramp-Down on Interface Error (SRD_ERR) .............................................. 54
7.7.5 Soft Ramp-Up on Recovered Interface Error (SRU_ERR) ................................. 54
7.7.6 Auto-Mute (AMUTE) ........................................................................................... 54
7.8 Master Volume Control - Integer (address 07h) .............................................................. 55
7.8.1 Master Volume Control - Integer (MSTR_IVOL[7:0]) .......................................... 55
7.9 Master Volume Control - Fraction (address 08h) ............................................................. 55
7.9.1 Master Volume Control - Fraction (MSTR_FVOL[1:0]) ....................................... 55
7.10 Channel XX Volume Control - Integer (addresses 09h - 0Eh) ....................................... 57
7.10.1 Channel Volume Control - Integer (CHXx_IVOL[7:0]) ...................................... 57
7.11 Channel XX Volume Control1 - Fraction (address 11h) .............................................. 57
7.12 Channel XX Volume Control2 - Fraction (address 12h) ................................................ 57
7.12.1 Channel Volume Control - Fraction (CHXX_FVOL[1:0]) ................................... 57
7.13 Channel Mute (address 13h) ......................................................................................... 58
7.13.1 Independent Channel Mute (CHXX_MUTE) ..................................................... 58
7.14 Channel Invert (address 14h) ........................................................................................ 58
7.14.1 Invert Signal Polarity (CHXX_INV) .................................................................... 58
7.15 Peak Limiter Control Register (address 15h) ............................................................... 59
7.15.1 Peak Signal Limit All Channels (LIMIT_ALL) .................................................... 59
7.15.2 Peak Signal Limiter Enable (LIMIT_EN) ........................................................... 59
7.16 Limiter Attack Rate (address 16h) ................................................................................ 59
7.16.1 Attack Rate (ARATE[7:0]) ................................................................................. 59
7.17 Limiter Release Rate (address 17h) ........................................................................... 60
7.17.1 Release Rate (RRATE[7:0]) .............................................................................. 60
7.18 Chnl XX Load Compensation Filter - Coarse Adjust (addresses 18h, 1Ah, 1Ch, 1Eh, 20h, 22h)
...................................................................................................................................... 60
7.18.1 Channel Compensation Filter - Coarse Adjust (CHXX_CORS[5:0]) ................. 60
7.19 Chnl XX Load Compensation Filter - Fine Adjust (addresses 19h, 1Bh, 1Dh, 1Fh, 21h, 23h)
...................................................................................................................................... 61
4
DS633PP1
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