Datasheet > CDP1853CEX

CDP1853CEX

更新时间： 2024-02-27 08:41:06

品牌	Logo	应用领域
英特矽尔 - INTERSIL		解码器逻辑集成电路光电二极管驱动
页数	文件大小	规格书
6页	36K
描述
N-Bit 1 of 8 Decoder

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技术参数
数据手册

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CDP1853CEX 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

CDP1853CEX 数据手册

CDP1853, CDP1853C

CDP1800 SERIES

N0 N1 N2 TPB MRD

TPA

TPB

V_DD

CLOCK A CLOCK B

CDP1853

CE N0 N1 N2

2-6

READ VIA

6F INSTRUCTION

CS1

CS2

CS1

CS2

CDP1852

OUTPUT

PORT 7

CDP1852

LOAD VIA 67

INPUT

DATA

INSTRUCTION

PORT 7

DATA AVAILABLE

STROBE

MODE

TPB

V_DD

CLOCK

5 CDP1852 INPUT AND OUTPUT PORTS

READ VIA

69 INSTRUCTION

CS2

CS1

CS2

CDP1852

LOAD VIA 61

OUTPUT

PORT 1

INPUT

DATA

INSTRUCTION

PORT 1

AVAILABLE

STROBE

MODE

TPB

V_DD

CLOCK

7 INPUT PORTS

7 OUTPUT PORTS

FIGURE 5. N-BIT DECODER IN A ONE-LEVEL I/O SYSTEM

CDP1800 SERIES

TPA TPB

NOTE: SYSTEM SHOWN WILL SELECT

UP TO 56 INPUT AND 48 OUTPUT

PORTS. WITH ADDITIONAL DECODING

THE TOTAL NUMBER OF INPUT

AND OUTPUT PORTS CAN BE

FURTHER EXPANDED.

NO, N1, N2

MRD BUS

DATA BUS

TPA

CL CSI

CS2

CDP1853

DECODED

“61” INSTRUCTION

INTERCONNECTED

AS IN FIGURE 4

CDP1852

CLOCK A

CLOCK B

I/O

7 INPUT

6 OUTPUT

CDP1853

“62-6F”

NO, N1, N2

PORTS

INST

CLOCK A

CLOCK B

I/O

7 INPUT

6 OUTPUT

CDP1853

“62-6F”

NO, N1, N2

PORTS

INST

SECTIONS 3-7

CLOCK A

CLOCK B

I/O

7 INPUT

6 OUTPUT

CDP1853

“62-6F”

NO, N1, N2

PORTS

INST

FIGURE 6. TWO-LEVEL I/O USING CDP1853 AND CDP1852

4-39

1 2 3 456

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与CDP1853CEX相关器件

型号	品牌	描述	获取价格	数据表
CDP1853D	INTERSIL	N-Bit 1 of 8 Decoder	获取价格
CDP1853D	RENESAS	OTHER DECODER/DRIVER, TRUE OUTPUT, CDIP16	获取价格
CDP1853D	ROCHESTER	Decoder/Driver, True Output, CMOS, CDIP16	获取价格
CDP1853D/3	ROCHESTER	OTHER DECODER/DRIVER, TRUE OUTPUT, CDIP16	获取价格
CDP1853D3	ROCHESTER	Decoder/Driver, True Output, CMOS, CDIP16	获取价格
CDP1853E	INTERSIL	N-Bit 1 of 8 Decoder	获取价格