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CDCL1810RGZT PDF预览

CDCL1810RGZT

更新时间: 2024-09-22 04:11:43
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器逻辑集成电路
页数 文件大小 规格书
25页 545K
描述
1.8V, 10 Output, High-Performance Clock Distributor

CDCL1810RGZT 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFN
包装说明:QFN-48针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1Is Samacsys:N
系列:1810输入调节:DIFFERENTIAL
JESD-30 代码:S-PQCC-N48JESD-609代码:e4
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.008 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:48实输出次数:10
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC48,.27SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法:TR峰值回流温度(摄氏度):260
电源:1.8 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.064 ns座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
最小 fmax:650 MHzBase Number Matches:1

CDCL1810RGZT 数据手册

 浏览型号CDCL1810RGZT的Datasheet PDF文件第2页浏览型号CDCL1810RGZT的Datasheet PDF文件第3页浏览型号CDCL1810RGZT的Datasheet PDF文件第4页浏览型号CDCL1810RGZT的Datasheet PDF文件第5页浏览型号CDCL1810RGZT的Datasheet PDF文件第6页浏览型号CDCL1810RGZT的Datasheet PDF文件第7页 
CDCL1810  
www.ti.com  
SLLS781AFEBRUARY 2007REVISED MARCH 2007  
1.8V, 10 Output, High-Performance Clock Distributor  
FEATURES  
Output Enable Control for Each Output  
SDA/SCL Device Management Interface  
48-pin QFN (RGZ) Package  
Single 1.8V Supply  
High-Performance Clock Distributor with 10  
Outputs  
Industrial Temperature Range: –40°C to +85°C  
Low Input-to-Output Additive Jitter:  
As Low As 10fs RMS  
APPLICATIONS  
Clock Synthesis and Distribution for  
High-Speed SERDES  
Synthesis and Distribution of SERDES  
Reference Clocks for 1G/10G Ethernet,  
1X/2X/4X/10X Fibre Channel, PCI Express,  
Serial ATA, SONET, CPRI, OBSAI, etc.  
Output Group Phase Adjustment  
Low-Voltage Differential Signaling (LVDS)  
Input, 100Differential On-Chip Termination,  
Up to 650MHz Frequency  
Differential Current Mode Logic (CML)  
Outputs, 50Single-Ended On-Chip  
Termination, Up to 650MHz Frequency  
Up to 1-to-10 Clock Buffering and Fan-out  
Two Groups of Five Outputs Each with  
Independent Frequency Division Ratios  
Output Frequency Derived with Divide Ratios  
of 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, and 80  
Meets ANSI TIA/EIA-644-A-2001 LVDS  
Standard Requirements  
Power Consumption: 410mW Typical  
5 Differential  
CML Outputs  
Up to 650MHz  
DIVIDER  
Differential  
LVDS Input  
Up to 650MHz  
5 Differential  
CML Outputs  
Up to 650MHz  
DIVIDER  
SDA/SCL  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007, Texas Instruments Incorporated  

CDCL1810RGZT 替代型号

型号 品牌 替代类型 描述 数据表
CDCL1810RGZRG4 TI

完全替代

1.8V, 10 Output, High-Performance Clock Distributor
CDCL1810RGZR TI

完全替代

1.8V, 10 Output, High-Performance Clock Distributor
CDCL1810RGZTG4 TI

完全替代

1.8V, 10 Output, High-Performance Clock Distributor

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