CDC3RL02BYFPR

更新时间： 2024-09-25 13:06:43

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CDC3RL02BYFPR 数据手册

CDC3RL02

www.ti.com

SCHS371 –NOVEMBER 2009

LOW PHASE-NOISE TWO-CHANNEL CLOCK FAN-OUT BUFFER

Check for Samples: CDC3RL02

FEATURES

APPLICATIONS

•

Cellular Phones

Global Positioning Systems (GPS)

Wireless LAN

FM Radio

WiMAX

•

Low Additive Noise:

–

–149 dBc/Hz at 10-kHz Offset Phase Noise

0.37-ps (RMS) Output Jitter

•

Limited Output Slew Rate for EMI Reduction

(1- to 5-ns/Rise/Fall Time for 10-pF to 50-pF

Loads)

W-BT

•

Adaptive Output Stage Controls Reflection

Regulated 1.8-V Externally Available I/O

Supply

•

Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP

(0.8 mm × 1.6 mm)

EESD Performance Exceeds JESD 22

–

2000-V Human-Body Model (A114-A)

1000-V Charged-Device Model

(JESD22-C101-A Level III)

YFP PACKAGE

(TOP VIEW)

Table 1. YFP PACKAGE TERMINAL

ASSIGNMENTS

V_BATT

V_LDO

CLK_OUT1

CLK_REQ1

CLK_REQ2

CLK_OUT2

MCLK_IN

GND

DESCRIPTION/ORDERING INFORMATION

The CDC3RL02 is a two-channel clock fan-out buffer. It buffers a single master clock, such as a temperature

compensated crystal oscillator (TCXO) to multiple peripherals. The device has two clock request inputs

(CLK_REQ1 and CLK_REQ2), each of which enable a single clock output.

The CDC3RL02 accepts square or sine waves at the master clock input (MCLK_IN), eliminating the need for an

AC coupling capacitor. The smallest acceptable sine wave is a 0.3-V signal (peak-to-peak). CDC3RL02 has been

designed to offer minimal channel-to-channel skew, additive output jitter, and additive phase noise. The adaptive

clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI

emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution

lines.

The CDC3RL02 has an integrated Low-Drop-Out (LDO) voltage regulator which accepts input voltages from 2.3

V to 5.5 V and outputs 1.8 V, 50 mA. This 1.8V supply is externally available to provide regulated power to

peripheral devices such as a TCXO.

The CDC3RL02 is ideal for use in portable end-equipment, such as mobile phones, that require clock buffering

with minimal additive phase noise and fan-out capabilities. It is offered in a 0.4-mm pitch wafer-level chip-scale

(WCSP) package (0.8 mm × 1.6 mm) and is optimized for very low standby current consumption.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...15

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与CDC3RL02BYFPR相关器件

型号	品牌	获取价格	描述	数据表
CDC3RL02YFPR	TI	获取价格	LOW PHASE-NOISE TWO-CHANNEL CLOCK FAN-OUT BUFFER
CDC3S04	TI	获取价格	Quad Sine-Wave Clock Buffer With LDO
CDC3S04YFFR	TI	获取价格	Quad Sine-Wave Clock Buffer With LDO
CDC4.4101.151	SCHURTER	获取价格	Mains Power Connector, 4A, 125/250VAC, Male, Solder Terminal, Socket, ROHS COMPLIANT
CDC4.4199.151	SCHURTER	获取价格	Mains Power Connector, 4A, 125/250VAC, Male, Solder Terminal, Socket, ROHS COMPLIANT
CDC421100	TI	获取价格	FULLY INTEGRATED FIXED FREQUENCY LOW-JITTER, CRYSTAL-OSCILLATOR CLOCK GENERATOR
CDC421100RGER	TI	获取价格	FULLY INTEGRATED FIXED FREQUENCY LOW-JITTER, CRYSTAL-OSCILLATOR CLOCK GENERATOR
CDC421100RGERG4	TI	获取价格	Fully Integrated Fixed Frequency Low-Jitter Crystal Oscillator Clock Generator 24-VQFN -40
CDC421100RGET	TI	获取价格	FULLY INTEGRATED FIXED FREQUENCY LOW-JITTER, CRYSTAL-OSCILLATOR CLOCK GENERATOR
CDC421100RGETG4	TI	获取价格	Fully Integrated Fixed Frequency Low-Jitter Crystal Oscillator Clock Generator 24-VQFN -40

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