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CD74HCT40105MG4 PDF预览

CD74HCT40105MG4

更新时间： 2024-01-05 05:26:20
品牌 Logo 应用领域
德州仪器 - TI 存储内存集成电路光电二极管先进先出芯片时钟
页数 文件大小 规格书
21页 461K
描述
High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register

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CD74HCT40105MG4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：GREEN, PLASTIC, SOIC-16针数：16
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.77
Is Samacsys：N最长访问时间：2250 ns
最大时钟频率 (fCLK)：12 MHz周期时间：100 ns
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：9.9 mm内存密度：64 bit
内存集成电路类型：OTHER FIFO内存宽度：4
湿度敏感等级：1功能数量：1
端子数量：16字数：16 words
字数代码：16工作模式：SYNCHRONOUS
最高工作温度：125 °C最低工作温度：-55 °C
组织：16X4可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：5 V
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：FIFOs最大压摆率：0.00016 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
Base Number Matches：1

CD74HCT40105MG4 数据手册

 浏览型号CD74HCT40105MG4的Datasheet PDF文件第1页浏览型号CD74HCT40105MG4的Datasheet PDF文件第3页浏览型号CD74HCT40105MG4的Datasheet PDF文件第4页浏览型号CD74HCT40105MG4的Datasheet PDF文件第5页浏览型号CD74HCT40105MG4的Datasheet PDF文件第6页浏览型号CD74HCT40105MG4的Datasheet PDF文件第7页 
CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105  
Three-State Outputs  
Pinout  
In order to facilitate data busing, three-state outputs (Q0 to  
CD54HC40105, CD54HCT40105  
(CERDIP)  
CD74HC40105, CD74HCT40105  
(PDIP, SOIC)  
Q3) are provided on the data output lines, while the load  
condition of the register can be detected by the state of the  
DOR output. A HIGH on the three-state control flag (output  
enable input OE) forces the outputs into the high-impedance  
OFF-state mode. Note that the shift-out signal, unlike that in  
the CD40105B, is independent of the three-state output  
control. In the CD40105B, the three-state control must not  
be shifted from High to Low when the shift-out signal is Low  
(data loss would occur). In the high-speed CMOS version  
this restriction has been eliminated.  
TOP VIEW  
THREE-STATE  
1
2
3
4
5
6
7
8
16 V  
CC  
CONTROL  
DIR  
15 SO  
14 DOR  
13 Q0  
12 Q1  
11 Q2  
10 Q3  
SI  
D0  
D1  
Cascading  
D2  
The 40105 can be cascaded to form longer registers simply  
by connecting the DIR to SO and DOR to SI. In the cascaded  
mode, a MASTER RESET pulse must be applied after the  
supply voltage is turned on. For words wider than four bits, the  
DIR and the DOR outputs must be gated together with AND  
gates. Their outputs drive the SI and SO inputs in parallel, if  
expanding is done in both directions (see Figures 12 and 13).  
D3  
9
MR  
GND  
Loading Data  
Data can be entered whenever the DATA-IN READY (DIR)  
flag is high, by a low to high transition on the SHIFT-IN (SI)  
input. This input must go low momentarily before the next  
word is accepted by the FIFO. The DIR flag will go low  
momentarily, until the data have been transferred to the sec-  
ond location. The flag will remain low when all 16-word loca-  
tions are filled with valid data, and further pulses on the SI  
input will be ignored until DIR goes high.  
Functional Diagram  
THREE-  
STATE  
CONTROL  
1
13  
4
Q0  
D0  
12  
5
Q1  
D1  
11  
Unloading Data  
6
7
Q2  
D2  
10  
As soon as the first word has rippled to the output, the data-  
out ready output (DOR) goes HIGH and data of the first word  
is available on the outputs. Data of other words can be  
removed by a negative-going transition on the shift-out input  
(SO). This negative-going transition causes the DOR signal  
to go LOW while the next word moves to the output. As long  
as valid data is available in the FIFO, the DOR signal will go  
high again, signifying that the next word is ready at the  
output. When the FIFO is empty, DOR will remain LOW, and  
any further commands will be ignored until a “1” marker  
ripples down to the last control register and DOR goes  
HIGH. If during unloading SI is HIGH, (FIFO is full) data on  
the data input of the FIFO is entered in the first location.  
Q3  
D3  
3
14  
2
DATA-OUT  
READY  
DATA-IN  
READY  
SHIFT IN  
15  
SHIFT OUT  
GND = 8  
= 16  
9
MASTER  
RESET  
V
CC  
Master Reset  
A high on the MASTER RESET (MR) sets all the control  
logic marker bits to “0”. DOR goes low and DIR goes high.  
The contents of the data register are not changed, only  
declared invalid, and will be superseded when the first word  
is loaded. Thus, MR does not clear data within the register  
but only the control logic. If the shift-in flag (SI) is HIGH  
during the master reset pulse, data present at the input (D0  
to D3) are immediately moved into the first location upon  
completion of the reset process.  
2
1234567...21

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