CD74HC40103QM96Q1

更新时间： 2024-10-01 02:59:59

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
12页	330K
描述
HIGH-SPEED CMOS LOGIC 8-STAGE SYCROOS,

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CD74HC40103QM96Q1 数据手册

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SCLS547A − OCTOBER 2003 − REVISED APRIL 2008

Qualified for Automotive Applications

Synchronous or Asynchronous Preset

Voltage = 2 V to 6 V

High Noise Immunity N or N = 30% of

, V

= 5 V

CC CC

Cascadable in Synchronous or Ripple

Mode

M PACKAGE

(TOP VIEW)

Fanout (Over Temperature Range)

− Standard Outputs . . . 10 LSTTL Loads

− Bus Driver Outputs . . . 15 LSTTL Loads

PE (SYNC)

Balanced Propagation Delay and Transition

Times

Significant Power Reduction Compared to

LSTTL Logic ICs

10 P4

PL (ASYNC)

GND

description/ordering information

The CD74HC40103 is manufactured with high-speed silicon-gate technology and consists of an 8-stage

synchronous down counter with a single output, which is active when the internal count is zero. The device

contains a single 8-bit binary counter. Each device has control inputs for enabling or disabling the clock, for

clearing the counter to its maximum count, and for presetting the counter either synchronously or

asynchronously. All control inputs and the terminal count (TC) output are active-low logic.

In normal operation, the counter is decremented by one count on each positive transition of the clock (CP)

output. Counting is inhibited when the terminal enable (TE) input is high. TC goes low when the count reaches

zero, if TE is low, and remains low for one full clock period.

When the synchronous preset enable (PE) input is low, data at the P0−P7 inputs are clocked into the counter on

the next positive clock transition, regardless of the state of TE. When the asynchronous preset enable (PL) input

is low, data at the P0−P7 inputs asynchronously are forced into the counter, regardless of the state of the PE, TE,

or CP inputs. Inputs P0−P7 represent a single 8-bit binary word for the CD74HC40103. When the master reset

(MR) input is low, the counter asynchronously is cleared to its maximum count of 255 , regardless of the state of

any other input. The precedence relationship between control inputs is indicated in the truth table.

If all control inputs except TE are high at the time of zero count, the counters jump to the maximum count, giving a

counting sequence of 100 or 256 clock pulses long.

{

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

‡

PACKAGE

−40°C to 125°C

SOIC − M

Tape and reel

CD74HC40103QM96Q1

HC40103Q

†

‡

For the most current package and ordering information, see the Package Option Addendum at the

end of this document, or see the TI web site at http://www.ti.com.

Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...12

中文翻译

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CD74HC40103QM96Q1 替代型号

型号	品牌	替代类型	描述	数据表
CD74HC40103QM96EP	TI	类似代替	HIGH-SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTER
74HC40103D,653	NXP	功能相似	74HC40103 - 8-bit synchronous binary down counter SOP 16-Pin

与CD74HC40103QM96Q1相关器件

型号	品牌	获取价格	描述	数据表
CD74HC40104E	RENESAS	获取价格	IC,SHIFT REGISTER,HC-CMOS,DIP,16PIN,PLASTIC
CD74HC40104EX	RENESAS	获取价格	CD74HC40104EX
CD74HC40104H	RENESAS	获取价格	暂无描述
CD74HC40104M96	RENESAS	获取价格	Parallel In Parallel Out, HC/UH Series, 4-Bit, Bidirectional, True Output, CMOS, PDSO16
CD74HC40105	TI	获取价格	High Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HC40105E	TI	获取价格	High Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HC40105E	ROCHESTER	获取价格	16X4 OTHER FIFO, 500ns, PDIP16
CD74HC40105EE4	TI	获取价格	High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register
CD74HC40105EX	RENESAS	获取价格	IC,FIFO,16X4,ASYNCHRONOUS,HC-CMOS,DIP,16PIN,PLASTIC
CD74HC40105EX	ROCHESTER	获取价格	16X4 OTHER FIFO, PDIP16

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