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CD74AC163MG4 PDF预览

CD74AC163MG4

更新时间： 2024-01-13 04:41:21
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
19页 579K
描述
Synchronous Presettable Binary Counters with Synchronous Reset 16-SOIC -55 to 125

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中文翻译

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CD74AC163MG4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP16,.25
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.46
其他特性：TCO OUTPUT计数方向：UP
系列：ACJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：9.9 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：73000000 Hz
最大I（ol）：0.012 A工作模式：SYNCHRONOUS
湿度敏感等级：1位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TUBE
峰值回流温度（摄氏度）：260电源：3.3/5 V
传播延迟（tpd）：207 ns认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Counters
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：1.5 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：3.9 mm最小 fmax：90 MHz
Base Number Matches：1

CD74AC163MG4 数据手册

 浏览型号CD74AC163MG4的Datasheet PDF文件第2页浏览型号CD74AC163MG4的Datasheet PDF文件第3页浏览型号CD74AC163MG4的Datasheet PDF文件第4页浏览型号CD74AC163MG4的Datasheet PDF文件第5页浏览型号CD74AC163MG4的Datasheet PDF文件第6页浏览型号CD74AC163MG4的Datasheet PDF文件第7页 
CD54AC163, CD74AC163  
4-BIT SYNCHRONOUS BINARY COUNTERS  
SCHS299B – APRIL 2000 – REVISED MARCH 2003  
CD54AC163 . . . F PACKAGE  
CD74AC163 . . . E OR M PACKAGE  
(TOP VIEW)  
Internal Look-Ahead for Fast Counting  
Carry Output for n-Bit Cascading  
Synchronous Counting  
CLR  
CLK  
A
V
CC  
RCO  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Synchronously Programmable  
Q
A
description/ordering information  
B
Q
B
The ’AC163 devices are 4-bit binary counters.  
These synchronous, presettable counters feature  
an internal carry look-ahead for application in  
high-speed counting designs. Synchronous  
operation is provided by having all flip-flops  
clocked simultaneously so that the outputs  
C
Q
C
D
Q
D
ENP  
GND  
ENT  
LOAD  
change, coincident with each other, when instructed by the count-enable (ENP, ENT) inputs and internal gating.  
This mode of operation eliminates the output counting spikes normally associated with synchronous  
(ripple-clock)counters. Abufferedclock(CLK)inputtriggersthefourflip-flopsontherising(positive-going)edge  
of the clock waveform.  
The counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.  
Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes  
the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.  
The clear function is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low  
after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear  
allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The  
active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000  
(LLLL).  
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without  
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.  
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a  
high-level pulse while the count is maximum (9 or 15, with Q high). This high-level overflow ripple-carry pulse  
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the  
level of CLK.  
These devices feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that  
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of  
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the  
stable setup and hold times.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – E  
Tube  
Tube  
CD74AC163E  
CD74AC163E  
CD74AC163M  
CD74AC163M96  
CD54AC163F3A  
–55°C to 125°C  
SOIC – M  
AC163M  
Tape and reel  
Tube  
CDIP – F  
CD54AC163F3A  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB  
design guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

中文翻译

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CD74AC163MG4 替代型号

型号 品牌 替代类型 描述 数据表
CD54AC163F3A TI

完全替代

 4-BIT SYNCHRONOUS BINARY COUNTERS
CD74AC163EE4 TI

完全替代

 Synchronous Presettable Binary Counters with Synchronous Reset 16-PDIP -55 to 125
CD74AC163M TI

完全替代

 4-BIT SYNCHRONOUS BINARY COUNTERS

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 		Serial In Parallel Out, AC Series, 8-Bit, Right Direction, True Output, CMOS, PDIP14
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 		Logic IC
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 		AC SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO14
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 		8-Bit Serial-In/Parallel-Out Shift Register

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