Datasheet > CD54HCT390

CD54HCT390

更新时间： 2024-01-01 23:59:55

品牌	Logo	应用领域
德州仪器 - TI		计数器
页数	文件大小	规格书
11页	267K
描述
High-Speed CMOS Logic Dual Decade Ripple Counter

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CD54HCT390 数据手册

CD74HC390,

CD54HCT390, CD74HCT390

Data sheet acquired from Harris Semiconductor

SCHS185C

High-Speed CMOS Logic

September 1997 - Revised October 2003

Dual Decade Ripple Counter

Features

Description

• Two BCD Decade or Bi-Quinary Counters

The CD74HC390 and ’HCT390 dual 4-bit decade ripple

counters are high-speed silicon-gate CMOS devices and are

pin compatible with low-power Schottky TTL (LSTTL). These

devices are divided into four separately clocked sections.

The counters have two divide-by-2 sections and two divide-

by-5 sections. These sections are normally used in a BCD

decade or bi-quinary conﬁguration, since they share a com-

mon master reset (nMR). If the two master reset inputs (1MR

and 2MR) are used to simultaneously clear all 8 bits of the

counter, a number of counting conﬁgurations are possible

within one package. The separate clock inputs (nCP0 and

nCP1) of each section allow ripple counter or frequency divi-

sion applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100.

Each section is triggered by the High-to-Low transition of the

input pulses (nCP0 and nCP1).

• One Package Can Be Conﬁgured to Divide-by-2, 4,

5,10, 20, 25, 50 or 100

[ /Title

(CD74

HC390

CD74

HCT39

/Sub-

ject

(High

Speed

CMOS

• Two Master Reset Inputs to Clear Each Decade

Counter Individually

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

For BCD decade operation, the nQ0 output is connected to

the nCP1 input of the divide-by-5 section. For bi-quinary

decade operation, the nO3 output is connected to the nCP0

• HC Types

- 2V to 6V Operation

input and nQ becomes the decade output.

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

at V

= 5V

The master reset inputs (1MR and 2MR) are active-High

asynchronous inputs to each decade counter which oper-

ates on the portion of the counter identiﬁed by the “1” and “2”

preﬁxes in the pin conﬁguration. A High level on the nMR

input overrides the clock and sets the four outputs Low.

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

IL IH

- CMOS Input Compatibility, I ≤ 1µA at V , V

Ordering Information

OL OH

TEMP. RANGE

PART NUMBER

CD54HCT390F3A

CD74HC390E

( C)

PACKAGE

16 Ld CERDIP

16 Ld PDIP

16 Ld SOIC

16 Ld PDIP

16 Ld SOIC

Pinout

-55 to 125

CD54HCT390

(CERDIP)

CD74HC390, CD74HCT390

(PDIP, SOIC)

CD74HC390M

TOP VIEW

CD74HC390MT

CD74HC390M96

CD74HCT390E

CD74HCT390M

CD74HCT390MT

CD74HCT390M96

1CP0

1MR

16 V

15 2CP0

14 2MR

13 2Q0

1CP1

12 2CP1

11 2Q

10 2Q

GND

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel

of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...11

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CD54HCT390 替代型号

型号	品牌	替代类型	描述	数据表
CD74HCT390	TI	功能相似	High Speed CMOS Logic Dual Decade Ripple Counter

与CD54HCT390相关器件

型号	品牌	获取价格	描述	数据表
CD54HCT390E	ETC	获取价格	Logic IC
CD54HCT390EN	ETC	获取价格	Logic IC
CD54HCT390F	RENESAS	获取价格	IC,COUNTER,UP,BI-QUINARY,HCT-CMOS,DIP,16PIN,CERAMIC
CD54HCT390F	ROCHESTER	获取价格	HCT SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, CDIP16
CD54HCT390F/3A	RENESAS	获取价格	IC HCT SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP DECADE COUNTER, CDIP16, CERAMIC, DIP-
CD54HCT390F3A	TI	获取价格	High-Speed CMOS Logic Dual Decade Ripple Counter
CD54HCT390F3A	RENESAS	获取价格	IC,COUNTER,UP,BI-QUINARY,HCT-CMOS,DIP,16PIN,CERAMIC
CD54HCT390H	RENESAS	获取价格	CD54HCT390H
CD54HCT390M	ETC	获取价格	Logic IC
CD54HCT393	TI	获取价格	High-Speed CMOS Logic Dual 4-Stage Binary Counter

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