Datasheet > CD54HCT10F3A

CD54HCT10F3A

更新时间： 2024-02-16 04:26:54

品牌	Logo	应用领域
德州仪器 - TI		触发器逻辑集成电路栅
页数	文件大小	规格书
10页	265K
描述
High-Speed CMOS Logic Triple 3-Input NAND Gate

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数据手册

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CD54HCT10F3A 数据手册

CD54HC10, CD74HC10,

CD54HCT10, CD74HCT10

Data sheet acquired from Harris Semiconductor

SCHS128C

High-Speed CMOS Logic

Triple 3-Input NAND Gate

August 1997 - Revised September 2003

Features

Description

[ /Title

(CD74

HC10,

CD74

HCT10

)

• Buffered Inputs

The ’HC10 and ’HCT10 logic gates utilize silicon gate CMOS

technology to achieve operating speeds similar to LSTTL

gates with the low power consumption of standard CMOS

integrated circuits. All devices have the ability to drive 10

LSTTL loads. The HCT logic family is functionally pin

compatible with the standard LS logic family.

• Typical Propagation Delay: 8ns at V

= 5V,

C = 15pF, T = 25 C

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

/Sub-

ject

Ordering Information

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

TEMP. RANGE

(High

Speed

CMOS

Logic

Triple

3-Input

NAND

Gate)

/Autho

r ()

/Key-

words

(High

Speed

CMOS

Logic

Triple

3-Input

NAND

Gate,

PART NUMBER

CD54HC10F3A

( C)

PACKAGE

14 Ld CERDIP

14 Ld PDIP

14 Ld SOIC

14 Ld PDIP

14 Ld SOIC

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

-55 to 125

CD54HCT10F3A

CD74HC10E

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

CD74HC10M

at V

= 5V

CD74HC10MT

CD74HC10M96

CD74HCT10E

CD74HCT10M

CD74HCT10MT

CD74HCT10M96

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V = 0.8V (Max), V = 2V (Min)

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel

of 250.

Pinout

CD54HC10, CD54HCT10

(CERDIP)

High

Speed

CMOS

Logic

Triple

3-Input

NAND

Gate,

CD74HC10, CD74HCT10

(PDIP, SOIC)

TOP VIEW

14 V

13 1C

12 1Y

11 3C

10 3B

Harris

Semi-

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

12 3 4 5 6 7...10

中文翻译

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与CD54HCT10F3A相关器件

型号	品牌	获取价格	描述	数据表
CD54HCT10H/3	RENESAS	获取价格	HCT SERIES, TRIPLE 3-INPUT NAND GATE, UUC14
CD54HCT10H/3A	RENESAS	获取价格	HCT SERIES, TRIPLE 3-INPUT NAND GATE, UUC14
CD54HCT10M	ETC	获取价格	Logic IC
CD54HCT11	TI	获取价格	High Speed CMOS Logic Triple 3-Input AND Gate
CD54HCT112	TI	获取价格	Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger
CD54HCT112E	ETC	获取价格	Logic IC
CD54HCT112EN	ETC	获取价格	Logic IC
CD54HCT112F	RENESAS	获取价格	HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
CD54HCT112F	ROCHESTER	获取价格	HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
CD54HCT112F/3	RENESAS	获取价格	HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16

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