CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
The frequency capture range (2f ) is defined as the
C
frequency range of input signals on which the PLL will lock if
V
V
V
=
(V /4π) (φSIG
CC
-
φCOMP )
IN
where
DEMOUT
DEMOUT
DEMOUT
IN
is the demodulator output at pin 10;
= V (via low-pass filter).
PC2OUT
it was initially out-of-lock. The frequency lock range (2f ) is
L
defined as the frequency range of input signals on which the
loop will stay locked if it was initially in lock. The capture
range is smaller or equal to the lock range.
The average output voltage from PC2, fed to the VCO via the
low-pass filter and seen at the demodulator output at pin 10
(V
), is the resultant of the phase differences of
DEMOUT
With PC1, the capture range depends on the low-pass filter SIG and COMP as shown in Figure 4. Typical waveforms
IN IN
characteristics and can be made as large as the lock range. for the PC2 loop locked at f are shown in Figure 5.
o
This configuration retains lock behavior even with very noisy
V
CC
input signals. Typical of this type of phase comparator is that
it can lock to input frequencies close to the harmonics of the
VCO center frequency.
V
DEMOUT (AV)
V
CC
1/2 V
CC
V
DEMOUT (AV)
1/2 V
CC
0
o
o
o
φDEMOUT
-360
0
360
FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
0
o
o
o
φDEMOUT
0
90
180
V
= V
DEMOUT
PC2OUT
= (V /4π) (φSIG - φCOMP );
CC IN IN
φ
= (φSIG - φCOMP )
FIGURE 2. PHASE COMPARATOR 1: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
DEMOUT IN IN
V
= V
= (V /π) (φSIG
= (φSIG - φCOMP
IN
-
)
IN
DEMOUT
PC1OUT
DEMOUT
CC
IN
φCOMP ); φ
IN
SIG
IN
COMP
IN
VCO
OUT
V
CC
PC2
OUT
SIG
GND
IN
HIGH IMPEDANCE OFF - STATE
COMP
IN
VCO
IN
VCO
OUT
PCP
OUT
PC1
OUT
FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 2, LOOP LOCKED AT f
V
CC
o
VCO
IN
GND
When the frequencies of SIG and COMP are equal but
IN IN
FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE
the phase of SIG leads that of COMP , the p-type output
IN IN
COMPARATOR 1, LOOP LOCKED AT f
o
driver at PC2
is held “ON” for a time corresponding to
OUT
the phase difference (φ
). When the phase of SIG
DEMOUT
lags that of COMP , the n-type driver is held “ON”.
IN
Phase Comparator 2 (PC2)
IN
When the frequency of SIG
is higher than that of
This is a positive edge-triggered phase and frequency
detector. When the PLL is using this comparator, the loop
is controlled by positive signal transitions and the duty
IN
COMP , the p-type output driver is held “ON” for most of
IN
the input signal cycle time, and for the remainder of the
cycle both n- and p-type drivers are “OFF” (three-state). If
the SIG frequency is lower than the COMP frequency,
factors of SIG and COMP are not important. PC2
IN IN
comprises two D-type flip-flops, control-gating and a three-
state output stage. The circuit functions as an up-down
IN
IN
then it is the n-type driver that is held “ON” for most of the
cycle. Subsequently, the voltage at the capacitor (C2) of
counter (Figure 1) where SIG causes an up-count and
IN
the low-pass filter connected to PC2
varies until the
COMP
a down-count. The transfer function of PC2,
OUT
signal and comparator inputs are equal in both phase and
IN
assuming ripple (f = f ) is suppressed, is:
r
i
4
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