Datasheet > CD-700-KAC-HEB-35.328

CD-700-KAC-HEB-35.328

更新时间： 2025-09-06 23:40:51

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
14页	143K
描述
Phase-Locked Loop

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中文翻译

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数据手册

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CD-700-KAC-HEB-35.328 数据手册

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CD-700

Complete VCXO based Phase Lock Loop

Features

• 5 x 7.5 x 2 mm, smallest VCXO PLL available

• Output Frequencies to 65.536MHz

• 5.0 or 3.3 Vdc operation

• Tri-State Output

• Loss of Signal Alarm

• VCXO with CMOS outputs

• 0/70 or –40/85 °C temperature range

• Hermetically sealed ceramic SMD package

Applications

• Frequency Translation

• Clock Smoothing, Clock Switching

• NRZ Clock recovery

LOS

(8)

PHO OPN

OPOUT VC

(1) (16)

LOSIN

(4)

• DSLAM, ADM, ATM, Aggregation, Optical

Switching/Routing, Base Station

• Low jitter PLL’s

(3)

(2)

OUT1

(13)

VCXO

DATAIN

(5)

OP-Amp

Phase

Description

Detector

and LOS

CLKIN

(6)

Optional

2N Divider

OUT2

(11)

The VI CD-700 is a user-configurable crystal

based PLL integrated circuit. It includes a digital

phase detector, op-amp, VCXO and additional

integrated functions for use in digital

synchronization applications. Loop filter software

is available as well SPICE models for circuit

simulation.

RCLK RDATA

OPP

(15)

GND VDD

(7) (14)

HIZ

(12)

(9)

(10)

Figure 1, CD-700 block diagram

Vectron International 166 Glover Avenue, Norwalk CT 06856-5160

Tel:1-88-VECTRON-1

e-mail: vectron@vectron.com

12 3 4 5 6 7...14

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