CAT9554, CAT9554A
START and STOP Conditions
FUNCTIONAL DESCRIPTION
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDAwhenSCLisHIGH. TheCAT9554/9554Amonitors
the SDA and SCL lines and will not respond until this
condition is met.
The CAT9554 and CAT9554A general purpose input/
output (GPIO) peripherals provide up to eight I/O ports,
controlled through an I2C compatible serial interface
The CAT9554/54A support the I2C Bus data transmis-
sion protocol. This I2C Bus protocol defines any device
that sends data to the bus to be a transmitter and any
device receiving data to be a receiver. The transfer is
controlled by the Master device which generates the
serial clock and all START and STOP conditions for bus
access. The CAT9554/9554A operate as a Slave de-
vice. Both the Master device and Slave device can
operate as either transmitter or receiver, but the Master
device controls which mode is activated.
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
Device Addressing
After the bus Master sends a START condition, a slave
address byte is required to enable the CAT9554/9554A
for a read or write operation. The four most significant
bits of the slave address are fixed as binary 0100 for the
CAT9554 (Figure 6) and as 0111 for the CAT9554A
(Figure7). TheCAT9554/9554Ausesthenextthreebits
as address bits.
I2C Bus Protocol
The features of the I2C bus protocol are defined as
follows:
The address bits A2, A1 and A0 are used to select which
device is accessed from maximum eight devices on the
same bus. These bits must compare to their hardwired
input pins. The 8th bit following the 7-bit slave address
is the R/W bit that specifies whether a read or write
operation is to be performed. When this bit is set to “1”,
a read operation is initiated, and when set to “0”, a write
operation is selected.
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition
(Figure 5).
Following the START condition and the slave address
byte, the CAT9554/9554A monitors the bus and re-
sponds with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
CAT9554/9554A then performs a read or a write opera-
tion depending on the state of the R/W bit.
SCL
SDA
START
STOP
CONDITION
CONDITION
Figure 5. START/STOP Conditions
SLAVE ADDRESS
SLAVE ADDRESS
0
1
1
1
A2
A1
A0 R/W
0
1
0
0
A2
A1
A0 R/W
FIXED
PROGRAMMABLE
HARDWARE
SELECTABLE
FIXED
PROGRAMMABLE
HARDWARE
SELECTABLE
Figure 6. CAT9554 Slave Address
Figure 7. CAT9554A Slave Address
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25088, Rev. B
8
5秒后页面跳转
SG3525资料手册详解：SG3525参数分析、引脚说明、应用介绍
AT89C51单片机资料手册详细解析及应用示例
CP2102资料手册解读：CP2102引脚说明、关键参数分析
资料手册解读：UC3842参数和管脚说明
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
