Datasheet > CAT9954AWI-T2

CAT9954AWI-T2

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
CATALYST		/
页数	文件大小	规格书
16页	267K
描述
8-bit I2C and SMBus I/O Port with Interrupt

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CAT9954AWI-T2 数据手册

CAT9554, CAT9554A

PIN CONFIGURATION

SOIC (W)

TSSOP (Y)

TQFN (HV4)

A1 A0

SDA

SCL

INT

SCL

INT

I/O0

I/O1

I/O2

I/O0

I/O1

I/O2

I/O3

I/O7

I/O6

I/O5

I/O4

I/O7

I/O6

I/O3

I/O4 I/O5

4 x 4 mm

Top View

PIN DESCRIPTION

SOIC / TSSOP

TQFN

PIN NAME

FUNCTION

A₀

A₁

Address Input 0

Address Input 1

Address Input 2

A₂

4-7

2-5

I/O_0-3

V_SS

I/O_4-7

INT

SCL

SDA

V_CC

Input/Output Port 0 to Input/Output Port 3

Ground

9-12

7-10

Input/Output Port 4 to Input/Output Port 7

Interrupt Output (open drain)

Serial Clock

Serial Data

Power Supply

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

V_CCwith Respect to Ground ............... –0.5V to +6.5V

V_SSSupply Current .......................................... 100mA

Voltage on Any Pin with

Package Power Dissipation

Respect to Ground ........................ –0.5V to +5.5V

Capability (T_A= 25°C) ................................... 1.0W

DC Current on I/O₀to I/O₇^{...........................................}+50 mA

DC Input Current............................................. +20 mA

V_CCSupply Current ............................................ 85mA

Junction Temperature ..................................... +150°C

Storage Temperature........................ -65°C to +150°C

RELIABILITY CHARACTERISTICS

Symbol

VZAP⁽²⁾

ILTH⁽²⁾⁽³⁾

Parameter

ESD Susceptibility

Latch-up

Reference Test Method

JEDEC Standard JESD 22

JEDEC Standard 17

Min

2000

100

Units

Volts

Notes:

(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this

specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

(2) This parameter is tested initially and after a design or process change that affects the parameter.

(3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to V +1V.

Characteristics subject to change without notice

Doc. No. 25088, Rev. B

123 4 5 6 7...16

下载PDF

与CAT9954AWI-T2相关器件

型号	品牌	描述	获取价格	数据表
CAT9954AYI-G-T2	CATALYST	8-bit I2C and SMBus I/O Port with Interrupt	获取价格
CAT9954AYI-T2	CATALYST	8-bit I2C and SMBus I/O Port with Interrupt	获取价格
CAT9954HV4I-G-T2	CATALYST	8-bit I2C and SMBus I/O Port with Interrupt	获取价格
CAT9954HV4I-T2	CATALYST	8-bit I2C and SMBus I/O Port with Interrupt	获取价格
CAT9954WI-G-T2	CATALYST	8-bit I2C and SMBus I/O Port with Interrupt	获取价格
CAT9954WI-T2	CATALYST	8-bit I2C and SMBus I/O Port with Interrupt	获取价格