Datasheet > CAT9954AHV4I-T2

CAT9954AHV4I-T2

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
CATALYST		/
页数	文件大小	规格书
16页	267K
描述
8-bit I2C and SMBus I/O Port with Interrupt

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数据手册

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CAT9954AHV4I-T2 数据手册

CAT9554, CAT9554A

The output port register sets the outgoing logic levels of

the I/O ports, defined as outputs by the configuration

pins defined as inputs. Reads from the output port

the output, not the actual I/O pin value.

the corresponding port pin as an input with a high

impedanceoutputdriver.Ifabitinthisregisteriscleared,

the corresponding port pin is enabled as an output. At

power-up, the I/Os are configured as inputs with a weak

pull-up resistor to V_CC

Data is transmitted to the CAT9554/9554A registers

using the write mode shown in Figure 9 and Figure 10.

The polarity inversion register allows the user to invert

the polarity of the input port register data. If a bit in this

inverted. If a bit in the polarity inversion register is

cleared (“0”), the original input port polarity is retained.

The CAT9554/9554A registers are read according to

the timing diagrams shown in Figure 11 and Figure 12.

Onceacommandbytehasbeensent, theregisterwhich

was addressed will continue to be accessed by reads

until a new command byte will be sent.

The configuration register sets the directions of the

ports. Set the bit in the configuration register to enable

SCL

SDA

slave address

A2 A1 A0

command byte

data to port

R/W

DATA 1

acknowledge from slave

acknowledge

from slave

acknowledge from slave

start condition

stop

condition

WRITE TO

PORT

DATA OUT

FROM PORT

DATA 1 VALID

Figure 9. Write to Output Port Register

SCL

SDA

slave address

A2 A1 A0

command byte

data to register

DATA 1

R/W

1/0

acknowledge from slave

acknowledge

from slave

stop

condition

start condition

WRITE TO

Figure 10. Write to Configuration or Polarity Inversion Register

Characteristics subject to change without notice

Doc. No. 25088, Rev. B

1...7 8 91011 12 13...16

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