Datasheet > CAT9554AWI-GT2

CAT9554AWI-GT2

更新时间： 2024-02-28 19:02:50

品牌	Logo	应用领域
安森美 - ONSEMI		外围集成电路光电二极管
页数	文件大小	规格书
16页	173K
描述
8-bit I²C and SMBus I/O Port with Interrupt

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CAT9554AWI-GT2 数据手册

CAT9554, CAT9554A

ACKNOWLEDGE

The command byte is the first byte to follow the device

address byte during a write/read bus transaction. The

which register will be written or read.

After a successful data transfer, each receiving device

is required to generate an acknowledge. The

acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8

bits of data. The SDA line remains stable LOW during

the HIGH period of the acknowledge related clock

pulse (Figure 5).

The input port register is a read only port. It reflects

the incoming logic levels of the I/O pins, regardless of

whether the pin is defined as an input or an output by

the configuration register. Writes to the input port

The CAT9554/9554A respond with an acknowledge

after receiving a START condition and its slave

address. If the device has been selected along with a

write operation, it responds with an acknowledge after

receiving each 8-bit byte.

Table 2. Register 0 – Input Port Register

bit

I₇

I₆

I₅

I₄

I₃

I₂

I₁

I₀

default

When the CAT9554/9554A begins a READ mode it

transmits 8 bits of data, releases the SDA line, and

monitors the line for an acknowledge. Once it receives

this acknowledge, the CAT9554/9554A will continue

to transmit data. If no acknowledge is sent by the

Master, the device terminates data transmission and

waits for a STOP condition. The master must then

issue a STOP condition to return the CAT9554/9554A

to the standby power mode and place the device in a

known state.

Table 3. Register 1 – Output Port Register

bit

O₇O₆O₅O₄O₃O₂O₁O₀

default

Table 4. Register 2 – Polarity Inversion Register

bit

N₇N₆N₅N₄N₃N₂N₁N₀

default

REGISTERS AND BUS TRANSACTIONS

Table 5. Register 3 – Configuration Register

The CAT9554/9554A consist of an input port register,

an output port register, a polarity inversion register

and a configuration register. Table 1 shows the

through Register 3 information.

bit

C₇C₆C₅C₄C₃C₂C₁C₀

default

Table 1. Register Command Byte

Command

Protocol

Function

(hex)

0x00

Read byte

Input port register

Output port register

0x01

0x02

0x03

Read/write byte

Polarity inversion register

Configuration register

BUS RELEASE DELAY (TRANSMITTER)

BUS RELEASE DELAY (RECEIVER)

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ACK SETUP

START

ACK DELAY

Figure 8. Acknowledge Timing

Characteristics subject to change without notice

Doc. No. MD-9002, Rev. F

1...6 7 8910 11 12...16

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与CAT9554AWI-GT2相关器件

型号	品牌	描述	获取价格	数据表
CAT9554AYI-G	ONSEMI	8-bit I²C and SMBus I/O Port with Interrupt	获取价格
CAT9554AYI-GT2	ONSEMI	8-bit I²C and SMBus I/O Port with Interrupt	获取价格
CAT9554HV4I	CATALYST	Parallel I/O Port, 8-Bit, 8 I/O, CMOS, 4 X 4 MM, ROHS COMPLIANT, MO-220, TQFN-16	获取价格
CAT9554HV4I-G	ONSEMI	8-bit I²C and SMBus I/O Port with Interrupt	获取价格
CAT9554HV4I-GT2	ONSEMI	8-bit I²C and SMBus I/O Port with Interrupt	获取价格
CAT9554HV4I-T2	CATALYST	Parallel I/O Port, 8-Bit, 8 I/O, CMOS, 4 X 4 MM, ROHS COMPLIANT, MO-220, TQFN-16	获取价格

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