5秒后页面跳转
CAT9554AWI-GT2 PDF预览

CAT9554AWI-GT2

更新时间: 2024-02-03 15:21:06
品牌 Logo 应用领域
安森美 - ONSEMI 外围集成电路光电二极管
页数 文件大小 规格书
16页 173K
描述
8-bit I²C and SMBus I/O Port with Interrupt

CAT9554AWI-GT2 数据手册

 浏览型号CAT9554AWI-GT2的Datasheet PDF文件第3页浏览型号CAT9554AWI-GT2的Datasheet PDF文件第4页浏览型号CAT9554AWI-GT2的Datasheet PDF文件第5页浏览型号CAT9554AWI-GT2的Datasheet PDF文件第7页浏览型号CAT9554AWI-GT2的Datasheet PDF文件第8页浏览型号CAT9554AWI-GT2的Datasheet PDF文件第9页 
CAT9554, CAT9554A  
PIN DESCRIPTION  
SCL: Serial Clock  
A0, A1, A2: Device Address Inputs  
The serial clock input clocks all data transferred into  
or out of the device. The SCL line requires a pull-up  
resistor if it is driven by an open drain output.  
These inputs are used for extended addressing  
capability. The A0, A1, A2 pins should be hardwired to  
VCC or VSS. When hardwired, up to eight  
CAT9554/9554As may be addressed on a single bus  
system. The levels on these inputs are compared with  
corresponding bits, A2, A1, A0, from the slave  
address byte.  
SDA: Serial Data/Address  
The bidirectional serial data/address pin is used to  
transfer all data into and out of the device. The SDA  
pin is an open drain output and can be wire-ORed  
with other open drain or open collector outputs. A pull-  
up resistor must be connected from SDA line to VCC.  
The value of the pull-up resistor, RP, can be calculated  
based on minimum and maximum values from Figure  
2 and Figure 3 (see Note).  
I/O0 to I/O7: Input / Output Ports  
Any of these pins may be configured as input or  
output. The simplified schematic of I/O0 to I/O7 is  
shown in Figure 4. When an I/O is configured as an  
input, the Q1 and Q2 output transistors are off  
creating a high impedance input with a weak pull-up  
resistor (typical 100k). If the I/O pin is configured as  
an output, the push-pull output stage is enabled. Care  
should be taken if an external voltage is applied to an  
I/O pin configured as an output due to the low  
impedance paths that exist between the pin and either  
VCC or VSS.  
I
= 3mA @ V  
Fast Mode I²C Bus / tr max - 300ns  
OL  
OLmax  
8.00  
7.00  
6.00  
5.00  
4.00  
3.00  
2.00  
1.00  
0.00  
2.5  
2
1.5  
1
0.5  
0
2
2.4 2.8 3.2 3.6  
4
4.4 4.8 5.2 5.6  
50  
100 150 200 250 300  
350 400  
V
(V)  
CC  
C
BUS  
(pF)  
Figure 2. Minimum RP Value versus  
Supply Voltage  
Figure 3. Maximum RP Value versus  
Bus Capacitance  
Note: According to the Fast Mode I²C bus specification, for bus capacitance up to 200pF, the pull up device can  
be a resistor. For bus loads between 200pF and 400pF, the pull-up device can be a current source (Imax = 3mA)  
or a switched resistor circuit.  
Doc. No. MD-9002 Rev. F  
6
© 2008 SCILLC. All rights reserved  
Characteristics subject to change without notice  

与CAT9554AWI-GT2相关器件

型号 品牌 描述 获取价格 数据表
CAT9554AYI-G ONSEMI 8-bit I²C and SMBus I/O Port with Interrupt

获取价格

CAT9554AYI-GT2 ONSEMI 8-bit I²C and SMBus I/O Port with Interrupt

获取价格

CAT9554HV4I CATALYST Parallel I/O Port, 8-Bit, 8 I/O, CMOS, 4 X 4 MM, ROHS COMPLIANT, MO-220, TQFN-16

获取价格

CAT9554HV4I-G ONSEMI 8-bit I²C and SMBus I/O Port with Interrupt

获取价格

CAT9554HV4I-GT2 ONSEMI 8-bit I²C and SMBus I/O Port with Interrupt

获取价格

CAT9554HV4I-T2 CATALYST Parallel I/O Port, 8-Bit, 8 I/O, CMOS, 4 X 4 MM, ROHS COMPLIANT, MO-220, TQFN-16

获取价格