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CAT9534HV4I-GT2

更新时间： 2024-01-22 09:50:00
品牌 Logo 应用领域
安森美 - ONSEMI 并行IO端口微控制器和处理器外围集成电路
页数 文件大小 规格书
16页 203K
描述
8-bit I²C and SMBus I/O Port with Interrupt

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CAT9534HV4I-GT2 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN, LCC16,.16SQ,25针数：16
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.58
Is Samacsys：NJESD-30 代码：S-XQCC-N16
JESD-609代码：e4长度：4 mm
湿度敏感等级：1位数：8
I/O 线路数量：8端口数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC16,.16SQ,25
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/5 V
认证状态：Not Qualified座面最大高度：0.8 mm
子类别：Parallel IO Port最大供电电压：5.5 V
最小供电电压：2.3 V标称供电电压：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4 mmuPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches：1

CAT9534HV4I-GT2 数据手册

 浏览型号CAT9534HV4I-GT2的Datasheet PDF文件第3页浏览型号CAT9534HV4I-GT2的Datasheet PDF文件第4页浏览型号CAT9534HV4I-GT2的Datasheet PDF文件第5页浏览型号CAT9534HV4I-GT2的Datasheet PDF文件第7页浏览型号CAT9534HV4I-GT2的Datasheet PDF文件第8页浏览型号CAT9534HV4I-GT2的Datasheet PDF文件第9页 
CAT9534  
PIN DESCRIPTION  
SCL: Serial Clock  
A0, A1, A2: Device Address Inputs  
The serial clock input clocks all data transferred into  
or out of the device. The SCL line requires a pull-up  
resistor if it is driven by an open drain output.  
These inputs are used for extended addressing  
capability. The A0, A1, A2 pins should be hardwired to  
VCC or VSS. When hardwired, up to eight CAT9534s  
may be addressed on a single bus system. The levels  
on these inputs are compared with corresponding bits,  
A2, A1, A0, from the slave address byte.  
SDA: Serial Data/Address  
The bidirectional serial data/address pin is used to  
transfer all data into and out of the device. The SDA  
pin is an open drain output and can be wire-ORed  
with other open drain or open collector outputs. A pull-  
up resistor must be connected from SDA line to VCC.  
The value of the pull-up resistor, RP, can be calculated  
based on minimum and maximum values from Figure  
2 and Figure 3 (see Note).  
I/O0 to I/O7: Input / Output Ports  
Any of these pins may be configured as input or  
output. The simplified schematic of I/O0 to I/O7 is  
shown in Figure 4. When an I/O is configured as an  
input, the Q1 and Q2 output transistors are off  
creating a high impedance input. If the I/O pin is  
configured as an output, the push-pull output stage is  
enabled. Care should be taken if an external voltage  
is applied to an I/O pin configured as an output due to  
the low impedance paths that exist between the pin  
and either VCC or VSS.  
I
= 3mA @ V  
Fast Mode I²C Bus / tr max - 300ns  
OL  
OLmax  
8.00  
7.00  
6.00  
5.00  
4.00  
3.00  
2.00  
1.00  
0.00  
2.5  
2
1.5  
1
0.5  
0
2
2.4 2.8 3.2 3.6  
4
4.4 4.8 5.2 5.6  
50  
100 150 200 250 300  
350 400  
V
(V)  
CC  
C
BUS  
(pF)  
Figure 2. Minimum RP Value versus  
Supply Voltage  
Figure 3. Maximum RP Value versus  
Bus Capacitance  
Note: According to the Fast Mode I²C bus specification, for bus capacitance up to 200pF, the pull up device can  
be a resistor. For bus loads between 200pF and 400pF, the pull-up device can be a current source (Imax = 3mA)  
or a switched resistor circuit.  
Doc. No. MD-9004 Rev. C  
6
© 2009 SCILLC. All rights reserved  
Characteristics subject to change without notice  
1...3456789...16

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