Datasheet > CAT34C02HU4I-G4

CAT34C02HU4I-G4

更新时间： 2022-04-25 19:13:59

品牌	Logo	应用领域
安森美 - ONSEMI		双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
14页	171K
描述
2 kb I2C EEPROM for DDR2 DIMM Serial Presence Detect TSSOPâ8 Y SUFFIX

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数据手册

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CAT34C02HU4I-G4 数据手册

CAT34C02

Read Operations

The address counter can be initialized by performing a

‘dummy’ Write operation (Figure 11). Here the START is

followed by the Slave address (with the R/W bit set to ‘0’)

and the desired byte address. Instead of following up with

Immediate Address Read

In standby mode, the CAT34C02 internal address counter

points to the data byte immediately following the last byte

accessed by a previous operation. If that ‘previous’ byte was

the last byte in memory, then the address counter will point

data, the Master then issues a 2 START, followed by the

‘Immediate Address Read’ sequence, as described earlier.

to the 1 memory byte, etc.

Sequential Read

If the Master acknowledges the 1 data byte transmitted

When, following a START, the CAT34C02 is presented

with a Slave address containing a ‘1’ in the R/W bit position

(Figure 10), it will acknowledge (ACK) in the 9 clock cycle,

and will then transmit data being pointed at by the internal

address counter. The Master can stop further transmission by

issuing a NoACK, followed by a STOP condition.

by the CAT34C02, then the device will continue

transmitting as long as each data byte is acknowledged by

the Master (Figure 12). If the end of memory is reached

during sequential Read, then the address counter will

‘wrap−around’ to the beginning of memory, etc. Sequential

Read works with either ‘Immediate Address Read’ or

‘Selective Read’, the only difference being the starting byte

address.

Selective Read

The Read operation can also be started at an address

different from the one stored in the internal address counter.

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

SDA LINE

DATA

SCL

SDA

8th Bit

DATA OUT

NO ACK

STOP

Figure 10. Immediate Address Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS (n)

SLAVE

ADDRESS

SDA LINE

DATA n

Figure 11. Selective Read Timing

BUS ACTIVITY:

SLAVE

ADDRESS

MASTER

DATA n

DATA n+1

DATA n+2

DATA n+x

SDA LINE

Figure 12. Sequential Read Timing

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