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CAT310W PDF预览

CAT310W

更新时间: 2024-02-05 08:57:41
品牌 Logo 应用领域
CATALYST 显示驱动器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
10页 375K
描述
10 Channel Automotive LED Display Driver

CAT310W 技术参数

是否Rohs认证: 符合生命周期:Lifetime Buy
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.15Is Samacsys:N
数据输入模式:SERIAL显示模式:SEGMENT
接口集成电路类型:LED DISPLAY DRIVERJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.8 mm
湿度敏感等级:3复用显示功能:NO
功能数量:1区段数:10
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified座面最大高度:2.64 mm
子类别:Display Drivers最大供电电压:5.5 V
最小供电电压:3 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mm最小 fmax:10 MHz
Base Number Matches:1

CAT310W 数据手册

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CAT310  
PIN DESCRIPTIONS  
VCC is the supply input for the internal logic  
and is compatible with both 3.3V and 5V  
systems. The logic is held in a reset state until  
VCC exceeds 2.5V. It is recommended that a  
small bypass ceramic capacitor (1uF) be  
placed between VCC and GND pins on the  
device.  
BLANK is the CMOS logic input (active high)  
used to temporarily disable all outputs. An  
internal pull-up current of 10 microampere is  
present on this pin. The BLANK pin must be  
driven to a logic low in order for channel outputs  
to resume normal operation. An external pull-  
down resistance of 10kor less is adequate for  
logic low.  
SIN is the CMOS logic pin for delivering the  
serial input data stream into the internal 10-bit  
shift register. The most recent or last data  
value in the serial stream is used to configure  
the state of output channel “zero” (OUT0).  
During the initial power up sequence all  
contents of the shift register are reset and  
cleared to zero.  
SOUT is the CMOS logic output used for daisy  
chain applications. The serial output data  
stream is fed from the last stage of the internal  
10-bit shift register. On each rising edge of the  
clock, the SOUT value will be updated. The  
data value present on this pin is identical to the  
data value being used for configuring the state  
of output channel nine (OUT9). At initial power  
up, the SOUT data stream will contain all  
zeroes until the shift register has been fully  
loaded.  
SCLK is the CMOS logic pin used to clock  
the internal shift register. On each rising edge  
of clock, the serial data will advance through  
one stage of the shift register.  
VBATT input monitors the battery voltage. If an  
over-voltage, above 19V typical, is detected, all  
outputs are disabled. Upon conclusion of the  
over-voltage condition, all outputs resume  
normal operation. The current drawn by the  
VBATT pin is less than 1 microampere during  
normal operation.  
XLAT is the CMOS logic input used to  
transfer data from the 10-bit shift register into  
the output channel latches. An internal pull-  
down current of 10 microampere is present on  
this pin. When XLAT is low, the state of each  
output channel remains unchanged. When  
XLAT is driven high, the contents of the shift  
register appear at their respective output  
channels. An external pull-up resistance of  
10kor less is adequate for logic high.  
OUT0-OUT9 are the ten LED outputs  
connected internally to the switch N-channel  
FETs. They sink currents up to 50mA per  
channel and can withstand transients up to 40V  
compatible with automotive “load dump”. The  
output on-resistance is 5, and the off-  
resistance is 5M.  
PGND, GND pins should be connected to  
the ground on the PCB.  
PIN TABLE  
Pin Number  
Pin Name  
SCLK  
Description/Function  
1
2
Clock input for the data shift register.  
Control input for the data latch.  
Serial data input.  
XLAT  
3
SIN  
4
SOUT  
Serial data output.  
5
GND  
Ground.  
6-10  
11-15  
16  
17  
18  
19  
20  
OUT4 - OUT0  
OUT9 - OUT5  
PGND  
Open drain outputs.  
Open drain outputs.  
Ground for LED driver outputs.  
Battery sense input.  
VBATT  
VCC  
Power supply voltage for the logic  
Blank input. When BLANK is high, all the output drivers are turned off.  
No connect.  
BLANK  
N.C.  
© 2005 Catalyst Semiconductor, Inc.  
4
Doc No. 25087, Rev. 00  
Characteristics subject to change without notice  

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