Datasheet > CAT24C161JI-42

CAT24C161JI-42

更新时间： 2024-01-21 05:42:23

品牌	Logo	应用领域
CATALYST		可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
页数	文件大小	规格书
12页	73K
描述
EEPROM, 2KX8, Serial, CMOS, PDSO8

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CAT24C161JI-42 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	SOP, SOP8,.25	Reach Compliance Code：	unknown
风险等级：	5.92	Is Samacsys：	N
数据保留时间-最小值：	100	耐久性：	1000000 Write/Erase Cycles
I2C控制字节：	1010MMMR	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e0	内存密度：	16384 bit
内存集成电路类型：	EEPROM	内存宽度：	8
端子数量：	8	字数：	2048 words
字数代码：	2000	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	2KX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	SERIAL
电源：	5 V	认证状态：	Not Qualified
串行总线类型：	I2C	最大待机电流：	0.00005 A
子类别：	EEPROMs	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	写保护：	HARDWARE
Base Number Matches：	1

CAT24C161JI-42 数据手册

Advanced Information

PIN DESCRIPTIONS

CAT24CXX1/XX2

WP: WRITE PROTECT

V_THthreshold and will continue driving the outputs for

approximately 200ms (t_PURST) after reaching V_TH.After

the t_PURSTtimeout interval, the device will cease to drive

reset outputs. At this point the reset outputs will be

pulled up or down by their respective pull up/pull down

devices. During power-down, the RESET outputs will

begin driving active when V_CCfalls below V_TH.The

RESET outputs will be valid so long as V_CCis >1.0V

(V_RVALID).

If the pin is tied to V_CCthe entire memory array becomes

WriteProtected(READonly). WhenthepinistiedtoV_SS

or left floating normal read/write operations are allowed

to the device.

SCL: SERIAL CLOCK

The serial clock input clocks all data transferred into or

out of the device.

RESET/RESET: RESET I/O

The RESET pins are I/Os; therefore, the CAT24CXXX

can act as a signal conditioning circuit for an externally

applied reset. The inputs are edge triggered; that is, the

RESET input in the 24CXXX will initiate a reset timeout

after detecting a low to high transition and the RESET

input in the 24CXXX will initiate a reset timeout after

detecting a high to low transition.

These are open drain pins and can be used as reset

triggerinputs. Byforcingaresetconditiononthepinsthe

device will initiate and maintain a reset condition for

approximately 200ms. RESET pin must be connected

through a pull-down and RESET pin must be connected

through a pull-up device.

Watchdog Timer

SDA: SERIAL DATA/ADDRESS

The bidirectional serial data/address pin is used to

transfer all data into and out of the device. The SDA pin

is an open drain output and can be wire-ORed with other

opendrainoropencollectoroutputs. Inthe24CXX1, the

SDA line is also used as the Watchdog Timer Monitor.

The Watchdog Timer provides an independent protec-

tion for microcontrollers. During a system failure, the

CAT24CXX1willrespondwitharesetsignalafteratime-

out interval of 1.6 seconds for lack of activity. 24CXX1

isdesignedwiththeWatchdogTimerfeatureontheSDA

input. For the 24CXX1, if the microcontroller does not

toggle the SDA input pin within 1.6 seconds the Watch-

dog Timer times out. This will generate a reset condition

onresetoutputs. The WatchdogTimerisclearedbyany

transition on SDA.

DEVICE OPERATION

Reset Controller Description

The CAT24CXXX provides a precision RESET control-

ler that ensures correct system operation during brown-

out and power-up/down conditions. It is configured

with open drain RESET outputs. During power-up, the

RESET outputs remain active until V_CCreaches the

As long as the reset signal is asserted, the Watchdog

Timer will not count and will stay cleared. 24CXX2 does

not feature the Watchdog Timer function.

Figure 1. RESET Output Timing

t_GLITCH

V_TH

RVALID

V_CC

t_RPD

t_PURST

RESET

t_RPD

RESET

Doc. No. 25079-00 8/99 M-1

1 2 3 456 7 8...12

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