CAT24CXX1/XX2
Advanced
ACKNOWLEDGE
location. The CAT24CXXX acknowledges once more
and the Master generates the STOP condition. At this
time,thedevicebeginsaninternalprogrammingcycleto
nonvolatile memory. While the cycle is in progress, the
device will not respond to any request from the Master
device.
Afterasuccessfuldatatransfer, eachreceivingdeviceis
requiredtogenerateanacknowledge.TheAcknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24CXXX responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
Page Write
The 24CXXX writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the
byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted, CAT24CXXX will respond with an
acknowledge, and internally increment the lower order
address bits by one. The high order bits remain un-
changed.
When the CAT24CXXX begins a READ mode it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24CXXX will continue to transmit
data. IfnoacknowledgeissentbytheMaster, thedevice
terminates data transmission and waits for a STOP
condition.
WRITE OPERATIONS
If the Master transmits more than 16 bytes before
sendingtheSTOPcondition,theaddresscounter‘wraps
around’,andpreviouslytransmitteddatawillbeoverwrit-
ten.
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
theSlavegeneratesanacknowledge, theMastersends
a 8-bit address that is to be written into the address
pointers of the CAT24CXXX. After receiving another
acknowledge from the Slave, the Master device trans-
mits the data to be written into the addressed memory
When all 16 bytes are received, and the STOP condi
tion has been sent by the Master, the internal program-
ming cycle begins. At this point, all received data is
written to the CAT24CXXX in a single write cycle.
Figure 7. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 8. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+15
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Doc. No. 25079-00 1/98 M-1
8