C9531

更新时间： 2024-01-26 18:02:49

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器 PC
页数	文件大小	规格书
10页	117K
描述
PCIX I/O System Clock Generator with EMI Control Features

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技术参数
数据手册

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C9531 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SSOP	包装说明：	SSOP-28
针数：	28	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.92	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e0	长度：	10.2 mm
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	133.33 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装等效代码：	SSOP28,.3	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	主时钟/晶体标称频率：	33.33 MHz
认证状态：	Not Qualified	座面最大高度：	2 mm
子类别：	Clock Generators	最大压摆率：	160 mA
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	5.3 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC	Base Number Matches：	1

C9531 数据手册

C9531

control signals is determined by the SMBus register Byte 0 bit

0. At initial power up this bit is set of a logic 1 state and thus

the frequency selections are controlled by the logic levels

present on the device’s S(0,1) pins. If the application does not

use an SMBus interface then hardware frequency selection

S(0,1) must be used. If it is desired to control the output clocks

using an SMBus interface, then this bit (B0b0) must first be set

to a low state. After this is done the device will use the contents

of the internal SMBus register Bytes 0 bits 3 and 4 to control

the output clock’s frequency.

Output Clock Three-state Control

All of the clocks in the Bank may be placed in a three-state

condition by bringing their relevant OE pins to a logic low state.

This transition to and from a three-state and active condition

is a totally asynchronous event and clock glitching may occur

during the transitioning states. This function is intended as a

board level testing feature. When output clocks are being

enabled and disabled in active environments the SMBus

control register bits are the preferred mechanism to control

these signals in an orderly and predictable manner.

The following formula and schematic may be used to under-

stand and calculate either the loading specification of a crystal

for a design or the additional discrete load capacitance that

must be used to provide the correct load to a known load rated

crystal.

The output enable pin contains an internal pull-up resistor that

will insure that a logic 1 is maintained and sensed by the

device if no external circuitry is connected to this pin.

Output Clock Frequency Control

All of the output clocks have their frequency selected by the

logic state of the S0 and S1 control bits. The source of these

(C_XINPCB+ C_XINFTG+ C_XINDISC) x (C_XOUTPCB) + C_XOUTFTG) + C_XOUTDISC

)

C_L=

(C_XINPCB+ C_XINFTG+ C_XINDISC) + (C_XOUTPCB) + C_XOUTFTG) + C_XOUTDISC

)

where:

C_XTAL

= The load rating of the crystal.

C_XINFTG= The clock generators XIN pin effective device internal capacitance to ground.

C_XOUTFTG= The clock generators XOUT pin effective device internal capacitance to ground.

C_XINPCB= The effective capacitance to ground of the crystal to device PCB trace.

C_XOUTPCB= The effective capacitance to ground of the crystal to device PCB trace.

C_XINDISC= Any discrete capacitance that is placed between the XIn pin and ground.

C_XOUTDISC= Any discrete capacitance that is placed between the XIn pin and ground.

XIN

C_XINPCB

C_XINDISC

C_XINFTG

C_XOUTPCB

C_XOUTDISC

C_XOUTFTG

XOUT

Clock Generator

As an example and using this formula for this data sheet’s

device, a design that has no discrete loading capacitors

(C_DISC) and each of the crystal device PCB traces has a

capacitance (C_PCB) to ground of 4 pF (typical value) would

calculate as:

(4 pF + 36 pF + 0 pF) x (4 pF + 36 pF + 0 pF)

1600

40 x 40

C_L=

= 20 pF.

Therefore, to obtain output frequencies that are as close to this

data sheets specified values as possible, in this design

example, you should specify a parallel cut crystal that is

designed to work into a load of 20 pF.

Document #: 38-07034 Rev. *D

Page 5 of 10

1 2 3 456 7 8...10

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