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C9531

更新时间： 2024-02-03 15:00:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器PC
页数 文件大小 规格书
10页 117K
描述
PCIX I/O System Clock Generator with EMI Control Features

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C9531 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP-28
针数：28Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.92JESD-30 代码：R-PDSO-G28
JESD-609代码：e0长度：10.2 mm
端子数量：28最高工作温度：70 °C
最低工作温度：最大输出时钟频率：133.33 MHz
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP28,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V主时钟/晶体标称频率：33.33 MHz
认证状态：Not Qualified座面最大高度：2 mm
子类别：Clock Generators最大压摆率：160 mA
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.3 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

C9531 数据手册

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C9531  
Pin Description[3]  
Pin[2]  
Name  
PWR[4]  
I/O  
Description  
3
XIN  
VDDA  
I
Crystal Buffer Input Pin. Connects to a crystal, or an external clock  
source. Serves as input clock TCLK, in Test mode.  
4
XOUT  
VDDA  
VDD  
O
O
I
Crystal Buffer Output Pin. Connects to a crystal only. When a Can  
Oscillator is used or in test mode, this pin is kept unconnected.  
1
REF  
OE  
Buffered inverted outputs of the signal applied at Xin, typically  
33.33 or 25.0 MHz.  
14*  
VDD  
Output Enable for Clock Bank. Causes the CLK (0:4) output clocks  
to be in a three-state condition when driven to a logic low level.  
24, 23, 22, 19, 18 CLK(0:4)  
VDDP  
VDD  
O
O
A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks.  
8
GOOD#  
When his output signal is a logic low level, it indicates that the output  
clocks of the bank are locked to the input reference clock. This  
output is latched.  
6*, 7*  
S(0,1)  
VDD  
I
Clock Bank Selection Bits. These control the clock frequency that will  
be present on the outputs of the bank of buffers. See table on page  
one for frequency codes and selection values.  
20, 25  
VDDP  
IA(0:2)  
SSCG#  
PWR 3.3V common power supply pin for all PCI clocks CLK (0:4).  
10*, 11*, 12*  
15*  
VDD  
VDD  
I
I
SMBus Address Selection Input Pins. See Table 3 on page 3.  
Spread Spectrum Clock Generator. Enables Spread Spectrum clock  
modulation when at a logic low level, see Spread Spectrum Clocking  
on page 6.  
28  
SDATA  
SCLK  
VDDA  
VDD  
VDD  
I/O  
Data for the Internal SMBus Circuitry. See Table 3 on page 3.  
Clock for the Internal SMBus Circuitry. See Table 3 on page 3.  
27  
I
I
13, 17  
Power for Internal Analog Circuitry. This supply should have a  
separately decoupled current source from VDD.  
2
VDD  
VSS  
PWR Power supply for internal core logic.  
PWR Ground pins for the device.  
5, 9, 16, 21, 26  
Notes:  
2. Pin numbers ending with * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is  
connected to them.  
3. A bypass capacitor (0.1µF) should be placed as close as possible to each VDD pin. If these bypass capacitors are not close to the pins their high frequency  
filtering characteristic will be cancelled by the lead inductance of the trace.  
4. PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s).  
Serial Data Interface  
Data Protocol  
To enhance the flexibility and function of the clock synthesizer,  
a two-signal serial interface is provided. Through the Serial  
Data Interface, various device functions, such as individual  
clock output buffers, can be individually enabled or disabled.  
The registers associated with the Serial Data Interface  
initializes to their default setting upon power-up, and therefore  
use of this interface is optional. Clock device register changes  
are normally made upon system initialization, if any are  
required.  
The clock driver serial protocol accepts block write a opera-  
tions from the controller. The bytes must be accessed in  
sequential order from lowest to highest byte (most significant  
bit first) with the ability to stop after any complete byte has  
been transferred. The C9531 does not support the Block Read  
function.  
The block write protocol is outlined in Table 2. The addresses  
are listed in Table 3.  
Document #: 38-07034 Rev. *D  
Page 2 of 10  
1234567...10

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