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C9531CT PDF预览

C9531CT

更新时间: 2024-01-03 14:54:36
品牌 Logo 应用领域
其他 - ETC 时钟发生器
页数 文件大小 规格书
14页 178K
描述
CPU SYSTEM CLOCK GENERATOR|TSSOP|28PIN|PLASTIC

C9531CT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP-28
针数:28Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.92JESD-30 代码:R-PDSO-G28
JESD-609代码:e0长度:10.2 mm
端子数量:28最高工作温度:70 °C
最低工作温度:最大输出时钟频率:133.33 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP28,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V主时钟/晶体标称频率:33.33 MHz
认证状态:Not Qualified座面最大高度:2 mm
子类别:Clock Generators最大压摆率:160 mA
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

C9531CT 数据手册

 浏览型号C9531CT的Datasheet PDF文件第2页浏览型号C9531CT的Datasheet PDF文件第3页浏览型号C9531CT的Datasheet PDF文件第4页浏览型号C9531CT的Datasheet PDF文件第5页浏览型号C9531CT的Datasheet PDF文件第6页浏览型号C9531CT的Datasheet PDF文件第7页 
APPROVED PRODUCT  
C9531  
PCIX I/O System Clock Generator With EMI Control Features  
Product Features  
Dedicated clock buffer power pins for reduced  
noise, crosstalk and jitter  
Test Mode Logic Table  
Buffer XIN Reference clock output  
Input clock frequency 33.3 MHz  
INPUT PINS  
OUTPUT PINS  
OE  
S1  
LOW  
LOW  
HIGH  
HIGH  
X
S0  
CLK(0:4)  
REF  
HIGH  
HIGH  
HIGH  
HIGH  
LOW  
LOW  
XIN  
XIN  
Output frequencies of 33.3, 66.6, 100 and 133.3  
MHz selectable (PCIX requirements)  
HIGH  
LOW  
HIGH  
X
2 * XIN  
3 * XIN  
4 * XIN  
Tri-State  
XIN  
XIN  
One output bank of 5 clocks.  
XIN  
SMBus clock control interface for individual clock  
disabling and SSCG control  
Tri-State  
Note: XIN is the frequency of the clock on the  
Output clock duty cycle is 50% (± 5%)  
<250 pS skew between output clocks within a  
bank  
device’s XIN pin.  
Output jitter <175 pSec.  
Spread Spectrum feature for reduced EMI  
OE pins for entire output bank enable control and  
testability  
28 Pin SSOP and TSSOP package  
Pin Configuration  
Block Diagram  
SSCG  
Logic  
CLK0  
CLK1  
SSCG#  
28  
REF  
VDD  
1
SDATA  
SCLK  
VSS  
27  
26  
25  
2
/N  
1
0
3
XIN  
XOUT  
VSS  
CLK2  
CLK3  
CLK4  
4
VDDP  
CLK0  
CLK1  
CLK2  
VSS  
24  
23  
22  
5
6
S0  
S1  
XIN  
OE  
7
GOOD#  
GOOD#  
VSS  
IA0  
8
21  
20  
19  
18  
17  
XOUT  
9
VDDP  
CLK3  
CLK4  
AVDD  
VSS  
REF  
10  
11  
12  
13  
14  
IA1  
SDATA  
SCLK  
IA2  
I2C  
Control  
Logic  
16  
15  
AVDD  
OE  
SSCG#  
IA(0:2)  
S(0,1)  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07034 Rev. **  
05/02/2001  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 1 of 14  

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