Datasheet > C9530CT

C9530CT

更新时间： 2024-02-15 12:45:39

品牌	Logo	应用领域
其他 - ETC		晶体时钟发生器外围集成电路光电二极管
页数	文件大小	规格书
14页	182K
描述
CPU SYSTEM CLOCK GENERATOR\|CMOS\|TSSOP\|48PIN\|PLASTIC

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C9530CT 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	TSSOP-48
针数：	48	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.88	JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e0	长度：	12.5 mm
端子数量：	48	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	133.33 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP48,.3,20	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	3.3 V	主时钟/晶体标称频率：	33.33 MHz
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	Clock Generators	最大压摆率：	30 mA
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	6.1 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC	Base Number Matches：	1

C9530CT 数据手册

APPROVED PRODUCT

C9530

PCIX I/O System Clock Generator With EMI Control Features

Test Table

These output frequencies will be present when SMBus byte 0 bit 7 has been set to a logic 0 state.

Test Function

Clock

Frequency

Outputs

CLKB(0:4)

XIN/4

CLKA(0:4)

XIN/6

REF

XIN

Table 3

Notes:

1. XIN is the frequency of the clock that is present on the XIN input during test mode.

Byte 1: A Bank and REF Clock Control Register

Byte 2: B Bank Clock Control Register

(1 = Enable, 0 = Stopped at a low level)

Bit

@Pup

Pin#

Description

Reserved

REF Enable/Stopped

CLKA4 Enable/Stopped

CLKA3 Enable/Stopped

CLKA2 Enable/Stopped

CLKA1 Enable/Stopped

CLKA0 Enable/Stopped

@Pup

Pin#

Description

Bit

Reserved

CLKB4 Enable/Stopped

CLKB3 Enable/Stopped

CLKB2 Enable/Stopped

CLKB1 Enable/Stopped

CLKB0 Enable/Stopped

Note: Stopping a clock indicated that the clock output is fixed in a logic low state. This effect will occur within 2 clock

cycles from the time the bit is set and does so in a manner so as not to cause any short or runt clock cycles. When the

stop is bit is changed from a stopped state to a running state the same (maximum 2 clock latency) delay occurs with the

first cycle being full in period (for the frequency that is selected

Internal Crystal Oscillator

This device will operate in two input reference clock configurations. In its simplest mode a 33.33 MHz fundamental cut

parallel resonant crystal is attached to the XIN and XOUT pins.

In the second mode a 33.33MHz input reference clock is driven in on the XIN clock from an external source. In this

application the XOUT pin must be left disconnected.

Output Clock Frequency Control

All of the output clocks have their frequency selected by the logic state of the S0 and S1 control bits. The source of

these control signals is determined by the SMBus register Byte 0 Bit 0. At initial power up this bit is set of a logic 1 state

and thus the frequency selections are controlled by the logic levels present on the devices SA(0,1) and SB(0,1) pins. If

the application does not use an SMBus interface then hardware frequency selection SA(0,1), (SB(0,1) that must be

used. If it is desired to control the output clocks using an SMBus interface, then this bit (Byte 0 Bit 0) must first be set to

a low state. After this is done the device will use the contents of the internal SMBus register Byte 0, Bits 1,2,3 and 4) to

control the output clock’s frequency.

Cypress Semiconductor Corporation

525 Los Coches St.

Document#: 38-07033 Rev. **

5/1/2000

Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571

http://www.cypress.com

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