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C-129-2500-FDFB-SLC2 PDF预览

C-129-2500-FDFB-SLC2

更新时间： 2024-01-22 22:50:06
品牌 Logo 应用领域
SOURCE 光纤通信
页数 文件大小 规格书
10页 819K
描述
2.5 Gbps Single Mode SFF LC Transceiver

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C-129-2500-FDFB-SLC2 技术参数

生命周期：ActiveReach Compliance Code：unknown
风险等级：5.75Is Samacsys：N
其他特性：2 X 5 ARRAY, IT ALSO OPERATES FROM 1100 NM TO 1620 NM主体宽度：13.6 mm
主体高度：9.8 mm主体长度或直径：48.8 mm
通信标准：GR-468, OC-48, SDH, SONET, STM-16连接类型：LC CONNECTOR
数据速率（接收）：2488 Mbps数据速率（发送）：2488 Mbps
发射极/检测器类型：LASER DIODE光纤设备类型：TRANSCEIVER
光纤类型：SMF安装特点：BOARD/PANEL MOUNT
最高工作温度：70 °C最低工作温度：
最大工作波长：1298 nm最小工作波长：1285 nm
标称工作波长：1290 nm标称光功率输出：0.562 mW
灵敏度：-20 dBm最大供电电压：3.5 V
最小供电电压：3.1 V标称供电电压：3.3 V
表面贴装：NOBase Number Matches：1

C-129-2500-FDFB-SLC2 数据手册

 浏览型号C-129-2500-FDFB-SLC2的Datasheet PDF文件第1页浏览型号C-129-2500-FDFB-SLC2的Datasheet PDF文件第2页浏览型号C-129-2500-FDFB-SLC2的Datasheet PDF文件第3页浏览型号C-129-2500-FDFB-SLC2的Datasheet PDF文件第5页浏览型号C-129-2500-FDFB-SLC2的Datasheet PDF文件第6页浏览型号C-129-2500-FDFB-SLC2的Datasheet PDF文件第7页 
2.5 Gbps Single Mode SFF LC Transceiver  
C-1XX-2500(C)-FDFB-SLCX  
Recommended Circuit Schematic  
Inputs to the C-1XX-2500(C)-FDFB-SLCX series transmitters are AC coupled and internally terminated through 50 ohms to AC ground.  
These transceivers can operate with LVPECL or CML logic levels. The input signal must have at least a 200 mV peak to (single ended) signal  
swing. Output from the receiver section of the module is also AC coupled and is expected to drive into 50 ohm load. Different termination  
strategies may be required depending on the particular Serializer / Deserializer chip set used.  
The C-1XX-2500(C)-FDFB-SLCX series product family are designed with AC coupled data inputs and outputs to provide the following  
advantages:  
■ Close positioning of SERDES with respect to transceiver; allows for shorter line lengths and at gigabit speeds reduces EMI.  
■ Minimum number of external components.  
■ Internal termination reduces the potential for unterminated stubs which would otherwise increase jitter and reduce transmission  
margin.  
Figure 1 & Figure 2 illustrates the recommended transmit and receive data line trminations for SERDES with CML and LVPECL Inputs / Outputs  
respectively.  
8
TX_DIS  
TTL logic level  
7
TX_GND  
TRANSMITTER  
Z=50�  
TD +  
TD -  
TX_D  
TX_D  
9
DRIVER  
Z=50�  
ꢀ0  
LASER  
Vcc_TX  
Vcc_RX  
6
2
Serializer / De-Serializer  
with CML lnputs/Outputs  
See  
Fig. 4A  
3
4
See  
SD  
Fig. 3  
BIAS  
Z=50�  
RD -  
RX_D  
TZ  
POST  
AMP  
PIN  
AMP  
Z=50�  
RD +  
RX_D  
5
ꢀ
RX_GND  
RECEIVER  
Note ꢀ  
Figure 1.Recommended TRANSMIT and RECEIVE Data Terminations for SERDES with CML I/Os.  
Note 1. Consult SERDES manufacturer’s data sheet and application data for appropriate receiver input biasing network.  
Some deserializer inputs are internally terminated and may not need external termination resistors.  
20550 Nordhoff St. • Chatsworth, CA 91311 • tel: 818.773.9044 • fax: 818.576.9486  
LUMINENTOIC.COM  
LUMNDS851-Jul2005  
rev. A.0  
9F, No 81, Shui Lee Rd. • Hsinchu, Taiwan, R.O.C. • tel: 886.3.5169222 • fax: 886.3.5169213  
4
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