Datasheet > BU7851FS-E2

BU7851FS-E2

更新时间： 2022-12-14 18:00:09

品牌	Logo	应用领域
罗姆 - ROHM		驱动器
页数	文件大小	规格书
25页	477K
描述
Serial / Parallel 4-input Drivers

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BU7851FS-E2 数据手册

Technical Note

BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS

【BU2050F】

●Pin descriptions

Pin No.

Pin Name

Function

Parallel Data Output

GND

VSS

Parallel Data Output

DATA

CLK

Serial Data Input

Clock Signal Input

Strobe Signal Input

STB

CLR

In case of “L”, the data of shift register outputs.

In case of “H”, all parallel outputs and data of latch circuit do not change.

Reset Signal Input

In case of “L”, the data of latch circuit reset, and all parallel output (P1～P8) can be L.

Normally CLR=H

Parallel Data output

Power Supply

VDD

●Timing chart

CLK

DATA8

DATA7

DATA6

DATA2

DATA1

DATA

CLR

STB

Previous DATA

DATA

“L”

Fig. 2

1. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 8 data bits into the

DATA pin.

2. Pn parallel output data of the shift register is set after the 8^thclock by the STB.

3. Since the STB is level latch, data is retained in the “L” section and renewed in the “H” section of the STB.

［Function explanation］

・

A latch circuit has the reset function, which is common in all bits. In case of CLR terminal is “L”, the latch

circuit is reset non-synchronously without the other input condition, and all parallel output can be “L”.

A serial data inputted from DATA terminal is read in shift register with synchronized rising of clock.

In case of STB is “L” (CLR is ”H”), transmit the data which read in the shift register to latch circuit, and

outputs from the parallel data output terminal (P1～P8).

・

In case of STB is “H”, all parallel outputs and the data of latch do not change.

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2009.06 - Rev.A

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