Datasheet > BU3883

BU3883

更新时间： 2024-10-01 23:36:07

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
7页	80K
描述
(78.61 k)

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中文翻译

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数据手册

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BU3883 数据手册

Video ICs

System control servo

BU38603 / BU38703 / BU38803

The BU38603, BU38703 and BU38803 are servo controller ICs for VCRs. They contain a high-speed, 8-bit CPU and

perform the processing required for the drum, capstan, FV and PV completely in software, allowing a large reduction

in the number of external components required. They also contain high-performance linear amplifiers, eliminating the

need for interface ICs. Specialized hardware is included for items that require high-speed processing, to allow

efficient utilization of the CPU.

Applications

•

VHS VCRs and camcorders

Features

1) CPU

•

9) Head amplifier / chroma rotary

Generated from pattern generator output.

10) Built-in AGC. Five-bits used to switch the gain

control registers for the CTL amplifier.

11) CTL counter: 1 / 30 or 1 / 25

12) Data shift PLL calculation: 24 bit

13) Timer: 8 bit × 2

499 commands (69 types)

Memory-mapped I / O

Minimum command execution time: 250ns (8MHz)

2)ROM capacity

BU38603: 16384 × 8 bit

BU38703: 24576 × 8 bit

BU38803: 32768 × 8 bit

3) RAM capacity: 512 × 8bit

4) Interrupt

14) Synchronous serial input/output: 8 bit × 1

15) VH PULSE

V separeted from composite synchronous snal.

Pseudo V generated from pattern generator

output.

Pattern generator: 1

Watch-dog timer: 1

External interrupts: 1

Superimposed pseudo H synchronized with

the composite synchronous signal.

16) VISS / VASS

FG interrupts: 5

Internal interrupts: 7

Two timers, serial transmission, interrupt, VHSW,

CTL interval timer (fixed) / VISS

Multi-layer interrupts possible.

5) Free-running counter: 19 bit

6) PWM output: 12 bit × 2

7) Pattern generator

VASS 0 / 1 discrimination

VISS discrimination threshold: 3

Aspect discrimination.

D / A CTL switching.

17) Standard I / O

Parallel I / O (PIO): 32 bit

17 bits from FRC MSB used.

Output

Parallel output (PO): 6 bit

18) A / D converter: 8 bits × 8 channels

Can be masked-programmed to be parallel inputs.

19) Watch-dog timer

Internal: 3 bit

External (PO): 5 bit

External (PIO): 6 bit

Setting period: 4

8) Programmable pre-scaler

CFG: 7 bit

20) Linear circuits

DFG: amplifier / comparator

CFG: amplifier / comparator

CTL: differential amplifier / comparator

DPG: comparator

CTL: 6 bit

12 3 4 5 6 7

中文翻译

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