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BSC9131CJN1KHKB PDF预览

BSC9131CJN1KHKB

更新时间: 2024-09-26 04:05:23
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
128页 1485K
描述
IC RISC PROCESSOR, Microprocessor

BSC9131CJN1KHKB 数据手册

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Freescale Semiconductor  
Data Sheet: Technical Data  
Document Number: BSC9131  
Rev. 0, 03/2014  
BSC9131  
BSC9131 QorIQ Qonverge  
Multicore Baseband  
Processor  
FC-PBGA–520  
21 mm x 21 mm  
The following list provides an overview of the feature set:  
• High-performance 32-bit e500 core built on Power  
Architecture® technology:  
– TCP/IP acceleration, quality of service, and  
classification capabilities  
– IEEE Std 1588™ support  
– eTSEC1 supports RGMII and RMII interfaces  
– eTSEC2 supports an RGMII interface  
• High-speed USB controller (USB 2.0)  
– Host and device support  
– 36-bit physical addressing  
– Double-precision floating-point support  
– 32-Kbyte L1 instruction cache and 32-Kbyte L1 data  
cache  
– Enhanced host controller interface (EHCI)  
– ULPI interface  
– Enhanced hardware and software debug support  
– 800 MHz/1 GHz clock frequency  
• Enhanced secure digital (SD/MMC) host controller  
(eSDHC)  
– 256-Kbyte L2 cache with ECC; also configurable as  
SRAM and stashing memory  
• Integrated Flash controller (IFC), supporting NAND,  
NOR, and general ASIC  
• One SC3850 core subsystem, which connects to the  
following:  
• TDM with one TDM port  
– 32 Kbyte 8-way level 1 data/instruction cache  
(L1 Dcache/ICache)  
– 512 Kbyte 8-way level 2 unified instruction/data cache  
(L2 cache/M2 memory)  
– Memory management unit (MMU)  
– Enhanced programmable interrupt controller (EPIC)  
– Debug and profiling unit (DPU)  
• Antenna interface controller (AIC), supporting three  
industry standard JESD/three custom parallel RF interfaces  
(two dual and one single port) and three MAXIM's  
MaxPHY serial interfaces  
• Universal Subscriber Identity Module (USIM) interface  
– Facilitates communication to SIM cards or Eurochip  
pre-paid phone cards  
– Two 32-bit quad timers  
• Four enhanced serial peripheral interfaces (eSPI)  
• Programmable interrupt controller (PIC) compliant with  
OpenPIC standard  
• Multi Accelerator Platform Engine for Femto Base Station  
Baseband Processing (MAPLE-B2F)  
– Supports variable sizes in Fourier Transforms,  
Convolution, Filtering, Turbo, Viterbi, Chiprate  
– Consists of accelerators for UMTS chip rate processing,  
LTE UP/DL channel processing, Matrix Inversion  
operations, and CRC algorithms  
• One four-channel DMA controller  
2
• Two I C interfaces  
• Two dual UART (DUART) interfaces  
• Two pulse-width modulator (PWM) interfaces  
• 96 general-purpose I/O signals  
• Eight 32-bit timers  
• DDR3/DDR3L SDRAM memory controller supports  
32-bit without ECC and 16-bit with ECC  
• Integrated security engine (ULE CAAM)  
– Protocol support includes DES, AES, RNG, CRC, MDE,  
PKE, SHA, and MD5  
• Operating temperature (Ta - T ) range: 0–105° C  
j
• Secure boot capability  
• Two enhanced three-speed Ethernet controllers (eTSECs)  
– 10/100/1000 Mbps support  
© 2014 Freescale Semiconductor, Inc. All rights reserved.  

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QorIQ Qonverge SoC, 800MHz StarCore DSP, 800MHz e500 CPU, MAPLE-B2F accelerator, DDR3, SEC