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BS62LV4008EIP70 PDF预览

BS62LV4008EIP70

更新时间: 2024-01-31 16:21:55
品牌 Logo 应用领域
BSI 静态存储器
页数 文件大小 规格书
10页 374K
描述
Very Low Power/Voltage CMOS SRAM 512K X 8 bit

BS62LV4008EIP70 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:TSOP2, TSOP32,.46Reach Compliance Code:unknown
风险等级:5.84最长访问时间:70 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G32
长度:20.95 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:32字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP32,.46封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
电源:2.5/3.3 V认证状态:Not Qualified
座面最大高度:1.2 mm最大待机电流:0.0000013 A
最小待机电流:1.5 V子类别:SRAMs
最大压摆率:0.025 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.4 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

BS62LV4008EIP70 数据手册

 浏览型号BS62LV4008EIP70的Datasheet PDF文件第4页浏览型号BS62LV4008EIP70的Datasheet PDF文件第5页浏览型号BS62LV4008EIP70的Datasheet PDF文件第6页浏览型号BS62LV4008EIP70的Datasheet PDF文件第8页浏览型号BS62LV4008EIP70的Datasheet PDF文件第9页浏览型号BS62LV4008EIP70的Datasheet PDF文件第10页 
BSI  
BS62LV4008  
(1,6)  
WRITE CYCLE2  
t
WC  
ADDRESS  
(11)  
t
CW  
(5)  
CE  
t
AW  
t
WP  
(2)  
WE  
t
AS  
(4,10)  
t
OW  
(7)  
(8)  
t
WHZ  
D OUT  
t
DW  
(8,9)  
t
DH  
D IN  
NOTES:  
1. WE must be high during address transitions.  
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals  
must be active to initiate a write and any one signal can terminate a write by going inactive.  
The data input setup and hold timing should be referenced to the second transition edge of  
the signal that terminates the write.  
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.  
4. During this period, DQ pins are in the output state so that the input signals of opposite phase  
to the outputs must not be applied.  
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE  
transition, output remain in a high impedance state.  
6. OE is continuously low (OE = VIL ).  
7. DOUT is the same phase of write data of this write cycle.  
8. DOUT is the read data of next address.  
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of  
opposite phase to the outputs must not be applied to them.  
10. The parameter is guaranteed but not 100% tested.  
11. TCW is measured from the later of CE going low to the end of write.  
Revision 1.1  
R0201-BS62LV4008  
7
Jan.  
2004  

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