Very Low Power/Voltage CMOS SRAM
128K x 16 or 256K x 8 bit switchable
BSI
BS616LV2025
DESCRIPTION
FEATURES
The BS616LV2025 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits or
262,144 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 4.5V to 5.5V supply voltage.
• Very low operation voltage : 4.5 ~ 5.5V
• Very low power consumption :
Vcc = 5.0V
C-grade: 40mA (Max.) operating current
I -grade: 45mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.6uA and maximum access time of 70/55 ns in 5V operation.
Easy memory expansion is provided by active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
• High speed access time :
-70
-55
70ns (Max.) at Vcc = 5.0V
55ns (Max.) at Vcc = 5.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS616LV2025 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
The BS616LV2025 is available in DICE form and 48-pin BGA type.
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
Vcc
PKG TYPE
( ICCSB1, Max )
( ICC, Max )
TEMPERATURE
RANGE
Vcc=5.0V
70 / 55
70 / 55
Vcc=5.0V
6uA
Vcc=5.0V
40mA
BS616LV2025DC
BS616LV2025AC
BS616LV2025DI
BS616LV2025AI
DICE
+0O C to +70O C
4.5V ~ 5.5V
4.5V ~ 5.5V
BGA-48-0608
DICE
-40O C to +85O
C
25uA
45mA
BGA-48-0608
BLOCK DIAGRAM
PIN CONFIGURATION
A15
A14
A13
A12
A11
A10
A9
Address
Input
20
1024
Row
Memory Array
1024 x 2048
Buffer
A8
Decoder
A7
A6
2048
Data
16(8)
16(8)
Column I/O
Input
D0
Buffer
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
16(8)
16(8)
128(256)
Data
Output
Buffer
Column Decoder
D15
CE1
CE2
14(16)
WE
OE
UB
Control
Address Input Buffer
LB
CIO
A16 A0 A1 A2 A3
A4 A5
(SAE)
Vdd
Vss
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.4
April 2002
R0201-BS616LV2025
1