Datasheet > BD99011EFV-M

BD99011EFV-M

更新时间： 2022-02-26 14:12:55

品牌	Logo	应用领域
罗姆 - ROHM		/
页数	文件大小	规格书
31页	1054K
描述
Simple Light Load Mode

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BD99011EFV-M 数据手册

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BD99010EFV-M, BD99011EFV-M

Block Diagram

VIN

4.5V

REG

1.2V

VREF

OSC

REG_L

For logic supply

For L-side FET driver

1.2V

FPWM

UVLO

TSD

IBIAS

PVIN

SLLM

Logic

0.8V

SCP

counter

Release

after 1024clk

SCP

OVP

1.2V

VOUT

LVS

DRV

LVIN

LOGIC

ERR

Detect Vin under 6V

VREGB

SLOPE

PWM

OVP

UVLO

TSD

COMP

OCP

Soft

Start

Current

Sense

GND

PGND

Figure 3. Block diagram

Description of Blocks

(1) Internal regulator voltage (REG)

This block generates the 4.5V supply of the internal circuitry. This function requires an external buffer capacitor

connected to the REG pin. Also the supply voltage has to be connected to the logic supply via the REG_L pin. A

ceramic capacitor with of 1μF or more or with low ESR with short leads to the REG, REG_L pin and ground is

recommended.

(2) Enable

By setting EN below 0.8V, the device can be set in stand-by mode. When the stand-by mode is activated, almost

all internal circuits are switched off to reduce the current consumption from the power supply to 1μA (25°C, typ.).

Because the EN pin is not pulled-down internally, in order to set the device in standby the EN pin has to be

connected to GND or supplied with the voltage below 0.8V. Moreover, EN sink current is below 0.1μA for

voltages to approximately 14V.

(3) FPWM

By setting FPWM pin more than 2.0V, the device switches to forced PWM mode and operates as normal

synchronous type DC/DC converter ie. no pulse skipping at low load conditions. With FPWM is disabled, the

quiescent current is very low but the step response is slow for large load step. With FPWM is enabled, the

quiescent current is larger but the step response is fast for large load step. Note that when the mode is changing

from SLLM to FPWM mode there will be an undershoot / over shoot. See Figure 27 on page 13 and Figure 31 on

page 14.

(4) Soft start

This block provides a function to prevent the overshoot of the output voltage: VOUT and/or large inrush currents

by controlling the error amplifier input voltage and increasing switching pulse width gradually at start up. The soft

start time is set to 6ms (typ.). At low output load conditions with FPWM is enabled, the soft start generates

some noise on the output voltage during sweep up to about 2 volts. This phenomenon can be avoided by adding

a small series resistance in the output buffer capacitor.

www.rohm.com

TSZ22111・15・001

TSZ02201-0W1W0AL00030-1-2

07.Jul.2014 Rev.003

3/28

1 234 5 6 7...31

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