4/4
〇NOTE FOR USE
１. When designing the external circuit, including adequate margins for variation between external devices
and IC. Use adequate margins for steady state and transient characteristics.
２. The circuit functionality is guaranteed within of ambient temperature operation range as long as it is
within recommended operating range. The standard electrical characteristic values cannot be guaranteed
at other voltages in the operating ranges, however the variation will be small.
３. Mounting failures, such as misdirection or miscounts, may harm the device.
４. A strong electromagnetic field may cause the IC to malfunction.
５. The GND pin should be the location within ±0.3V compared with the PGND pin.
６. BD9890F and BD9890FV incorporate a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown
circuit (TSD circuit) is designed only to shut the IC off to prevent runaway thermal operation. It is not
designed to protect the IC or guarantee its operation of the thermal shutdown circuit is assumed.
７. Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become
significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical
countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings.
８. About the external FET, theparasitic Capacitor may cause the gate voltage to change, when the drain voltage
is switching. Make sure to leave adequate margin for this IC variation.
９. On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch.
１０. By STB voltage, BD9890F and BD9890FV are changed to 2 states. Therefore, do not input STB pin voltage
between one state and the other state (0.8～1.6).
１１. The pin connected a connector need to connect to the resistor for electrical surge destruction.
This IC is a monolithic IC which (as shown is Fig-1) has P+ substrate and between the various pins.
A P-N junction is formed from this P layer of each pin. For example, the relation between each potential
is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can
result in mutual interference among circuits as well as operation faults and physical damage. Accordingly
you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than
the GND (P substrate) voltage to an input pin.
１２．This IC is a monolithic IC which (as shown is Fig-1)has P+ substrate and between the various pins. A
P-N junction is formed from this P layer of each pin. For example, the relation between each potential
is as follows,
○(When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.)
○(When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.)
Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can
result in mutual interference among circuits as well as operation faults and physical damage. Accordingly
you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than
the GND (P substrate) voltage to an input pin.
Transistor (NPN)
Resistance
B
(PinA)
(PinB)
E
C
GND
N
N
P＋
P＋
P
N
N
P substrate
GND
Parasitic diode
P substrate
GND
Parasitic diode
(PinB)
(PinA)
Parasitic diode
E
GND
GND
Other adjacent components
Parasitic diode
Fig-1 Simplified structure of a Bipolar IC
REV. A
5秒后页面跳转
PCF8574资料解读：主要参数分析、引脚说明
AD637数据手册解读：主要特性、引脚及其功能解读、电气参数
ADUM1201资料手册解读：参数分析、引脚说明、应用分析
一文带你了解压敏电阻器在直流电路中的过压保护作用
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
