BD4860FVE-TR

更新时间： 2024-02-14 23:50:17

品牌	Logo	应用领域
罗姆 - ROHM		/
页数	文件大小	规格书
10页	259K
描述
Power Supply Support Circuit, Fixed, 1 Channel, +6VV, CMOS, PDSO5, ROHS COMPLIANT, VSOF-5

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BD4860FVE-TR 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SSOP
包装说明：	ROHS COMPLIANT, SSOP-5	针数：	5
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	7 weeks
风险等级：	0.73	Base Number Matches：	1

BD4860FVE-TR 数据手册

Technical Note

BD48□□G, BD48□□FVE, BD49□□G, BD49□□FVE series

 Reference Data

Examples of Leading (TPLH) and Falling (TPHL) Output

Part Number

BD4845G/FVE

BD4945G/FVE

TPLH (μs)

39.5

TPHL (μs)

87.8

32.4

52.4

VDD=4.3V5.1V

VDD=5.1V4.3V

*This data is for reference only.

The figures will vary with the application, so please confirm actual operating conditions before use.

 Explanation of Operation

For both the open drain type (Fig.12) and the CMOS output type (Fig.13), the detection and release voltages are used as

threshold voltages. When the voltage applied to the VDD pins reaches the applicable threshold voltage, the VOUT terminal

voltage switches from either “High” to “Low” or from “Low” to “High”. Because the BD48□□G/FVE series uses an open drain

output type, it is possible to connect a pull-up resistor to VDD or another power supply [The output “High” voltage (VOUT) in

this case becomes VDD or the voltage of the other power supply].

VDD

Vref

VOUT

GND

Fig.12 (BD48□□ Type Internal Block Diagram)

Fig.13 (BD49□□ Type Internal Block Diagram)

 Timing Waveform

Example: the following shows the relationship between the input voltages VDD and the output voltage VOUT when the

input power supply voltage VDD is made to sweep up and sweep down (the circuits are those in Fig.12 and 13).

When the power supply is turned on, the output is unsettled from

after over the operating limit voltage (VOPL) until TPHL. There fore it

V^DET+ΔV^DET

is possible that the reset signal is not outputted when the rise time of

VDD is faster than TPHL.

⑤

V^DET

When VDD is greater than VOPL but less than the reset release

V^OPL

voltage (VS + ∆VS), the output voltages will switch to Low.

If VDD exceeds the reset release voltage (VS + ∆VS), then

OUT

VOUT switches from L to H.

V^OH

If VDD drops below the detection voltage (VS) when the power

T^PLH

T^PHL

PLH

supply is powered down or when there is a power supply fluctuation,

VOUT switches to L (with a delay of TPHL).

T^PHL

V^OL

The potential difference between the detection voltage and the

①

②

③

④

release voltage is known as the hysteresis width (∆VS). The system

is designed such that the output does not flip-flop with power supply

fluctuations within this hysteresis width, preventing malfunctions due

to noise.

Fig.14

www.rohm.com

2009.04 - Rev.A

5/9

1 2 3 456 7 8...10

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与BD4860FVE-TR相关器件

型号	品牌	描述	获取价格	数据表
BD4860G	ROHM	Voltage Detector IC	获取价格
BD4860G-TL	ROHM	Standard CMOS Voltage Detector IC	获取价格
BD4860G-TR	ROHM	Standard CMOS Voltage Detector IC	获取价格
BD487	INFINEON	PNP SILICON PLANAR TRANSISTORS	获取价格
BD488	INFINEON	PNP SILICON PLANAR TRANSISTORS	获取价格
BD48E23	ROHM	Standard CMOS Voltage Detector IC	获取价格

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