Technical Note
BD4154FV
●Block Diagram
3.3V/1.30A
V3-1
V3-2
V3_IN1
4
5
6
7
VD
3.3V
V3_IN2
TSD,CL,UVLO
VD
3.3V AUX/275mA
V3AUX
V3AUX_IN
18
17
3.3V
TSD,CL,UVLO_AUX
V15_IN1
V15_IN2
1.5V/625mA
V15-1
V15-2
15
16
14
19
1.5V
V3AUX_IN
VD
CPPE#
CPUSB#
SYSR
12
Input
logic
RCLKEN
11
3
Power
good
TSD,CL,UVLO
PERST#
EN,SYSR,CPUSB#,CPPE#
8
1
TSD
V3AUX_IN
Thermal
PERST_IN#
protection
V3_IN,V3AUX_IN,V15_IN
V3,V3AUX,V15
CL
EN
Reference
Block
V3_IN
2
Under
V3AUX_IN
VD
UVLO
voltage
lock out
Charge
Pump
V15_IN
UVLO_AUX
10
GND
●PIN CONFIGRATION
●PIN FUNCTION
PIN No
PIN NAME
PIN FUNCTION
PERST_IN#
EN
1
2
20
NC
1
2
PERST_IN# PERST# control input pin (SysReset#)
EN
SYSR
Enable input pin
Logic input pin
V3 input pin 1
V3 input pin 2
V3 output pin 1
V3 output pin 2
Logic output pin
Test pin
19
RCLKEN
3
3
18
17
16
15
14
13
12
11
SYSR
4
V3_IN1
V3_IN2
V3_1
V3AUX_IN
V3AUX
V15_IN2
V15_IN1
V15_2
5
V3_IN1
V3_IN2
4
6
7
V3_2
5
8
PERST#
TEST
9
V3_1
V3_2
6
10
11
12
13
14
15
16
17
18
GND
GND pin
7
CPUSB#
CPPE#
V15_1
Logic input pin
Logic input pin
V15 output pin 1
V15 output pin 2
V15 input pin 1
V15 input pin 2
V3AUX output pin
8
PERST#
V15_1
V15_2
9
TEST
GND
CPPE#
V15_IN1
V15_IN2
V3AUX
V3AUX_IN
10
CPUSB#
V3AUX input pin 1
SSOP-B20 Package
Reference clock enable signal/
Power good signal (No delay)
Non connection
19
20
RCLKEN
NC
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2009.05 - Rev.A
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