BD4153FV,BD4153EFV
Technical Note
●Reference data
V3AUX
V3
V3AUX
V3
V3AUX
V3
CP#
CP#
CP#
SYSR
SYSR
SYSR
Fig. System Stand-by⇔Active
Fig.1 System Stand-by→Active
Fig.2 System Active⇔Stand-by
(No Card)
(Card)
(Card)
V3AUX
CPUSB#
V3AUX
V3
V3
V3
CP#
CP#
V3AUX
PERST#
SYSR
SYSR
Fig.6 USB Card Assert/ DeAssert
(Active)
Fig.4 PCI Card Assert/DeAssert
(Stand-by)
Fig.5 Card Assert/DeAssert
(Active)
V3 rise propagation delay TIME
V3 RISETIME
10000
PERST#
V3
10000
1000
100
1000
100
10
1
10
1
SS_V3
0.1
0.1
Logic Input(SYSR)
1.00E-10
1.00E-09
1.00E-08
1.00E-07 1.00E-06
1.00E-06
1.00E-07
1.00E-10
1.00E-09
1.00E-08
0.01
0.01
CSS_V3 (F)
CSS_V3 (F)
Fig.7 V3 RISETIME
Fig.8 V3 rise
Fig.9 V3 Start up
Propagation delay TIME
(Stand-by→Active)
V3AUX RISE TIME
10000
PERST#
V3
PERST#
V3
1000
100
10
1
SS_V3
SS_V3
0.1
Logic Input(CP#)
Logic Input(EN)
1.00E-10
0.01
1.00E-09
1.00E-08
1.00E-07
CSS_V3AUX (F)
Fig.10 V3 Start up
(Card Assert)
Fig.11 V3 Wave Form
(Shut down→Active)
Fig.12 V3AUX
RISE TIME
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2010.04 - Rev.B
4/17
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