List of Figures
Figure 3.1
BlueCore4-Audio ROM Device Pinout........................................................................................ 11
BlueCore4-Audio ROM Device Diagram..................................................................................... 43
BlueCore HCI Stack.................................................................................................................... 47
BlueCore RFCOMM Stack.......................................................................................................... 50
Virtual Machine ........................................................................................................................... 52
HID Stack.................................................................................................................................... 53
Circuit RF_P and RF_N .............................................................................................................. 55
Circuit RX_IN .............................................................................................................................. 56
TCXO Clock Accuracy ................................................................................................................ 58
Crystal Driver Circuit................................................................................................................... 61
Crystal Equivalent Circuit............................................................................................................ 61
Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency...................... 65
Crystal Driver Transconductance vs. Driver Level Register Setting ........................................... 66
Crystal Driver Negative Resistance as a Function of Drive Level Setting .................................. 67
Universal Asynchronous Receiver.............................................................................................. 68
Break Signal................................................................................................................................ 69
UART Bypass Architecture ......................................................................................................... 70
USB Connections for Self-Powered Mode.................................................................................. 72
USB Connections for Bus-Powered Mode.................................................................................. 73
USB_DETACH and USB_WAKE_UP Signal.............................................................................. 74
SPI Write Operation.................................................................................................................... 76
SPI Read Operation.................................................................................................................... 76
BlueCore4-Audio ROM CODEC Diagram................................................................................... 77
BlueCore4-Audio ROM Microphone Biasing............................................................................... 78
Differential Microphone Input...................................................................................................... 78
Single-ended Microphone Input.................................................................................................. 79
Speaker Output........................................................................................................................... 79
Frequency Response of the ADC and DAC Pair ........................................................................ 80
Simulated Wind Noise Reduction Filter Response ..................................................................... 81
Audio CODEC Outline and Applicable Gains ............................................................................. 82
Spectrum of Analogue and Digital ADC Output with a Full Scale Sine Wave Input ................... 85
Spectrum of DAC Output with 1kHz Full Scale Tone.................................................................. 86
Spectrum of DAC Output with 1kHz Tone at -42dB Relative to Full Scale................................. 87
Response of CVSD Interpolation/Decimation Filter.................................................................... 88
BlueCore4-Audio ROM as PCM Interface Master ...................................................................... 89
BlueCore4-Audio ROM as PCM Interface Slave ........................................................................ 90
Long Frame Sync (Shown with 8-bit Companded Sample)........................................................ 90
Short Frame Sync (Shown with 16-bit Sample).......................................................................... 91
Multi-slot Operation with Two Slots and 8-bit Companded Samples.......................................... 91
GCI Interface............................................................................................................................... 92
16-Bit Slot Length and Sample Formats..................................................................................... 93
PCM Master Timing Long Frame Sync....................................................................................... 95
PCM Master Timing Short Frame Sync ...................................................................................... 95
PCM Slave Timing Long Frame Sync......................................................................................... 96
PCM Slave Timing Short Frame Sync ........................................................................................ 97
Example TCXO Enable OR Function........................................................................................ 101
Maximum Transmit Power vs. Temperature (20 DH5 Packets)................................................ 106
Firmware Controlled Transmit Power vs. Temperature (20 DH5 Packets)............................... 107
Transmit Power Variation and Mean vs. Channel (20 DH5 Packets) ....................................... 107
-20dB Bandwidth vs. Temperature (DH5 Packets)................................................................... 108
Figure 7.1
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
Figure 10.7
Figure 10.8
Figure 10.9
Figure 10.10
Figure 10.11
Figure 10.12
Figure 10.13
Figure 10.14
Figure 10.15
Figure 10.16
Figure 10.17
Figure 10.18
Figure 10.19
Figure 10.20
Figure 10.21
Figure 10.22
Figure 10.23
Figure 10.24
Figure 10.25
Figure 10.26
Figure 10.27
Figure 10.28
Figure 10.29
Figure 10.30
Figure 10.31
Figure 10.32
Figure 10.33
Figure 10.34
Figure 10.35
Figure 10.36
Figure 10.37
Figure 10.38
Figure 10.39
Figure 10.40
Figure 11.1
Figure 11.2
Figure 11.3
Figure 11.4
This Material is Subject to CSR's
Non-Disclosure Agreement
Production Information
© CSR plc 2006
BC413159A-db-001Pi
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