B10011S-MFPG1

更新时间： 2024-02-24 13:19:21

品牌	Logo	应用领域
爱特美尔 - ATMEL		电信集成电路光电二极管异步传输模式 ATM
页数	文件大小	规格书
11页	116K
描述
CAN TRANSCEIVER IC

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B10011S-MFPG1 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP, SOP16,.25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.75
Is Samacsys：	N	数据速率：	250 Mbps
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
长度：	9.9 mm	湿度敏感等级：	1
功能数量：	1	端子数量：	16
收发器数量：	1	最高工作温度：	105 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	电源：	5,7/32 V
认证状态：	Not Qualified	座面最大高度：	1.75 mm
子类别：	Network Interfaces	标称供电电压：	5 V
表面贴装：	YES	电信集成电路类型：	INTERFACE CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	3.8 mm	Base Number Matches：	1

B10011S-MFPG1 数据手册

B10011S

The implementation of a power filter and overvoltage clamp as follows is highly

recommended:

Figure 6. Implementation of a Power Filter and Over Clamps

From battery

(cl. 15)

To V_CC(pin 13)

To pin 10

22 µF

33 V

Ground

Application Hints

As an interface between CAN controllers and a two-wire data bus system for serial data

interchange, this device is adapted to a special high-level, low-speed transmission sys-

tem, which is useful in harsh environments. High immunity against ground offset and

interference voltages on the bus have been the design goals for this device, rather than

low power consumption or a minimum of external components. An error detection

scheme is implemented in the receiver part to give quick information to the controller in

case of faults occurring on the bus. Thus, the controller is able to start a search cycle in

order to look for the possibility of single-wire operation or to disable the station from the

bus.

An automatic error-signal end is not feasible because parts of the system are disabled

during single-wire operation. Therefore, the controller has to carry out short tests by

switching to the two-wire state and checking, whether the error signal is still present or

not. Errors due to dirty contacts, shorts between high and low line, or interruptions may

not be recognized at all, because this device does not contain a complete fault

computer.

Two control inputs A_seland B_selenable four operation modes (see Table “Operating

Modes” on page 3’). Depending on the nature of the error, the error signal ER is inter-

nally generated partly in the recessive or partly in the dominant transmission state. In

order to avoid watching the error bits bitwise, an open-collector output driver (with a

1-kW series resistor) discharges a storage capacitor, which is charged by a time con-

stant, long enough to hold the 0 state for, e.g., 200 µs, thus, giving the controller enough

time to recognize this status during idle times. Only the charging resistor may be

changed and not the 2.2-nF capacitor. In order to perform a faster error-end test, the

charging resistor may be shorted by an NPN emitter follower or by a tristate output high

for approximately 1 to 2 µs.

The pinout of the device shows a controller side (pins 1 to 8) and a bus side (pins 9 to

16). The application circuit utilizes an input filter section which is necessary for every

station and a bias section which is needed in two master stations only. Additional slave

stations only contain the driving resistors at pins 11 and 12 (270 Ω and 220 Ω), the

choke coil, and capacitor between pins 13 and 10.

A power filter and overvoltage clamp is highly recommended in order to avoid transmis-

sion errors due to spikes on the 24-V battery voltage.

The input filter is designed as an 2-RC filter for 125 kbit/s and may be changed to

250 kbit/s. Its good pulse response and good suppression of high frequencies should

not be weakened by omitting one of the capacitors.

4749B–AUTO–09/04

1...4 5 678 9 10 11

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