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AU5790D-T PDF预览

AU5790D-T

更新时间: 2024-02-09 23:38:01
品牌 Logo 应用领域
飞利浦 - PHILIPS 电信信息通信管理光电二极管电信集成电路
页数 文件大小 规格书
25页 127K
描述
CAN Transceiver, 1-Trnsvr, BICMOS, PDSO8,

AU5790D-T 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:SOP, SOP8,.25Reach Compliance Code:unknown
风险等级:5.81Is Samacsys:N
数据速率:100 MbpsJESD-30 代码:R-PDSO-G8
JESD-609代码:e4端子数量:8
收发器数量:1最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:12 V认证状态:Not Qualified
子类别:Network Interfaces最大压摆率:45 mA
标称供电电压:12 V表面贴装:YES
技术:BICMOS电信集成电路类型:CAN TRANSCEIVER
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

AU5790D-T 数据手册

 浏览型号AU5790D-T的Datasheet PDF文件第4页浏览型号AU5790D-T的Datasheet PDF文件第5页浏览型号AU5790D-T的Datasheet PDF文件第6页浏览型号AU5790D-T的Datasheet PDF文件第8页浏览型号AU5790D-T的Datasheet PDF文件第9页浏览型号AU5790D-T的Datasheet PDF文件第10页 
Philips Semiconductors  
Application note  
AU5790 Single wire CAN transceiver  
AN2005  
3.2 Block Diagram and Function Description  
The AU7590 consists of several functional blocks shown in the block diagram below.  
BATTERY (+12V)  
BAT  
1
VOLTAGE  
TEMP.  
PROTECTION  
REFERENCE  
L
BUS  
CANH  
TxD  
7
OUTPUT  
BUFFER  
CAN  
CONTROLLER  
AND  
µC  
C
UL  
3
NSTB  
(Mode 0)  
MODE  
BUS  
CONTROL  
6
RECEIVER  
EN  
(Mode 1)  
R
T
RxD  
5
4
LOSS OF  
GROUND  
RTH  
(LOAD)  
PROTECTION  
AU5790  
8
GND  
SL01306  
Figure 6. AU5790 block diagram  
The protocol controller feeds the transmit data stream to the transceiver’s TxD input. The AU5790 transceiver converts the TxD data input to a  
bus signal with controlled slew rate and wave-shaping to minimize electromagnetic emissions. The bus output signal is transmitted via the  
CANH in/output pin, which is connected to the physical bus medium. If TxD is low, then a typical voltage of 4 V is output at the CANH pin. If TxD  
is high then the CANH output is pulled passive low via the local bus load resistance R . The physical bus lines for all transceivers on the bus are  
T
connected in a wired-OR configuration, therefore the bus will be at a dominant level unless all nodes in network are passive.  
To provide protection against a disconnection of the module ground wire the resistor R is connected to the RTH pin of the AU5790. The RTH  
T
pin is connected to ground via the loss of ground protection circuit in the AU5790. By providing this switched ground pin, no current can flow  
from the floating module ground to the bus via load resistor R .  
T
The bus receiver detects the data stream at the bus line. The data signal is output at the RxD pin, which should be connected to a CAN  
controller. If the bus level is recessive, i.e. all transmitters are passive, then RxD is floating or High with external pull-up resistance. If the bus  
6
2001 Apr 16  

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