Datasheet > ATR4255P

ATR4255P

更新时间： 2022-02-26 12:20:59

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
34页	386K
描述
FM Double-conversion System

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ATR4255P 数据手册

3.2

Test Mode

A special test mode is implemented for final production test only. This mode is activated by set-

ting bit 9 to “1”. This mode is not intended to be used in customer applications. For normal

operation, bit 9 has to be set to “0”. Bits 18 to 30 are deactivated in normal operation mode.

Table 3-2.

Test Mode

Mode

Bit 9

Normal operation

Test mode

3.3

3.4

VCO

An oscillator circuit is implemented to build a VCO as proposed in the application schematic. The

VCO frequency is used to generate the LO frequency of the 1^stmixer stages. The control voltage

of the VCO is usually generated by the PLL circuit ATR4256. The VCO signal is provided at the

buffered output pin 16 to be fed to the PLL circuit.

FM RF-AGC

The FM RF-AGC circuit includes a wideband level detector at the input, pin 1, of the FM mixer,

and an in-band level detector at the output of the FM IF amplifier (pin 30). The outputs of these

level detectors are used to control the current into the pin diode (see Figure 3-1) in order to limit

the signal level at the FM mixer input and the following stages. The maximum pin diode current

is determined by R115 and the time constant of the AGC control loop can be adjusted by chang-

ing the value of C111.

The AGC threshold level at the input of the FM mixer can be adjusted by bits 64 and 65 as

shown in Table 3-3. The in-band AGC threshold referred to the FM mixer input (pin 1, pin 2)

depends on the gain of the FM IF amplifier and can be adjusted using bits 89 to 91.

Figure 3-1. FM RF-AGC Bit 92

Pin 42

Pin 5

C111

R115

PIN Diode

AGC

B92

ATR4255P

4883B–AUDR–01/06

1...3 4 567 8 9...34

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