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ATR0621-7FQY PDF预览

ATR0621-7FQY

更新时间: 2024-01-06 17:26:50
品牌 Logo 应用领域
爱特美尔 - ATMEL 电信集成电路蜂窝电话电路电信电路全球定位系统异步传输模式ATM
页数 文件大小 规格书
20页 394K
描述
GPS Baseband Processor

ATR0621-7FQY 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:LFBGA,针数:100
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.83JESD-30 代码:S-PBGA-B100
长度:9 mm功能数量:1
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH认证状态:Not Qualified
座面最大高度:1.4 mm标称供电电压:1.8 V
表面贴装:YES技术:CMOS
电信集成电路类型:BASEBAND CIRCUIT温度等级:INDUSTRIAL
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM宽度:9 mm
Base Number Matches:1

ATR0621-7FQY 数据手册

 浏览型号ATR0621-7FQY的Datasheet PDF文件第1页浏览型号ATR0621-7FQY的Datasheet PDF文件第2页浏览型号ATR0621-7FQY的Datasheet PDF文件第3页浏览型号ATR0621-7FQY的Datasheet PDF文件第5页浏览型号ATR0621-7FQY的Datasheet PDF文件第6页浏览型号ATR0621-7FQY的Datasheet PDF文件第7页 
2. Architectural Overview  
2.1  
Description  
The ATR0621 architecture consists of two main buses, the Advanced System Bus (ASB) and  
the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter-  
faces the processor with the on-chip 32-bit memories and the external memories and devices  
by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip  
peripherals and is optimized for low power consumption. The AMBA Bridge provides an inter-  
face between the ASB and the APB.  
An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip  
USARTs/SPI and the on-chip and off-chip memories without processor intervention. Most  
importantly, the PDC2 removes the processor interrupt handling overhead and significantly  
reduces the number of clock cycles required for a data transfer. It can transfer up to 64K con-  
tiguous bytes without reprogramming the starting address. As a result, the performance of the  
microcontroller is increased and the power consumption reduced.  
The ATR0621 peripherals are designed to be easily programmable with a minimum number of  
instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of  
the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address  
space.) The peripheral base address is the lowest address of its memory space. The periph-  
eral register set is composed of control, mode, data, status, and interrupt registers.  
To maximize the efficiency of bit manipulation, frequently written registers are mapped into  
three memory locations. The first address is used to set the individual register bits, the second  
resets the bits, and the third address reads the value stored in the register. A bit can be set or  
reset by writing a “1” to the corresponding position at the appropriate address. Writing a “0”  
has no effect. Individual bits can thus be modified without having to use costly read-modify-  
write and complex bit-manipulation instructions.  
All of the external signals of the on-chip peripherals are under the control of the Parallel I/O  
(PIO2) Controller. The PIO2 Controller can be programmed to insert an input filter on each pin  
or generate an interrupt on a signal change. After reset, the user must carefully program the  
PIO2 Controller in order to define which peripheral signals are connected with off-chip logic.  
The ARM7TDMI® processor operates in little-endian mode on the ATR0621 GPS Baseband.  
The processor's internal architecture and the ARM® and Thumb® instruction sets are  
described in the ARM7TDMI datasheet. The memory map and the on-chip peripherals are  
described in detail in the ATR0621 full datasheet. The electrical and mechanical characteris-  
tics are also documented in the ATR0621 full datasheet.  
The ARM standard In-Circuit Emulation debug interface is supported via the JTAG/ICE port of  
the ATR0621.  
Features of the ROM firmware are described in software documentation available from u-blox  
AG.  
4
ATR0621 [Preliminary]  
4890AS–GPS–09/05  

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