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ATF16V8B/BQ/BQL PDF预览

ATF16V8B/BQ/BQL

更新时间: 2022-01-18 22:57:00
品牌 Logo 应用领域
其他 - ETC 可编程逻辑器件
页数 文件大小 规格书
19页 549K
描述
ATF16V8B/BQ/BQL [Updated 4/01. 19 Pages] 250 gate electrically erasable PLD. 20 pins

ATF16V8B/BQ/BQL 数据手册

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ATF16V8B(QL)  
In simple mode all feedback paths of the output pins are  
routed via the adjacent pins. In doing so, the two inner most  
pins (pins 15 and 16) will not have the feedback option as  
these pins are always configured as dedicated combinato-  
rial output.  
Macrocell Configuration  
Software compilers support the three different OMC  
modes as different device types. Most compilers have the  
ability to automatically select the device type, generally  
based on the register usage and output enable (OE) usage.  
Register usage on the device forces the software to choose  
the registered mode. All combinatorial outputs with OE  
controlled by the product term will force the software to  
choose the complex mode. The software will choose the  
simple mode only when all outputs are dedicated combina-  
torial without OE control. The different device types can be  
used to override the automatic device selection by the soft-  
ware. For further details, refer to the compiler software  
manuals.  
ATF16V8B Registered Mode  
PAL Device Emulation/PAL Replacement. The registered  
mode is used if one or more registers are required. Each  
macrocell can be configured as either a registered or com-  
binatorial output or I/O, or as an input. For a registered  
output or I/O, the output is enabled by the OE pin, and the  
register is clocked by the CLK pin. Eight product terms are  
allocated to the sum term. For a combinatorial output or  
I/O, the output enable is controlled by a product term, and  
seven product terms are allocated to the sum term. When  
the macrocell is configured as an input, the output enable is  
permanently disabled.  
When using compiler software to configure the device, the  
user must pay special attention to the following restrictions  
in each mode.  
In registered mode pin 1 and pin 11 are permanently  
configured as clock and output enable, respectively. These  
pins cannot be configured as dedicated inputs in the  
registered mode.  
Any register usage will make the compiler select this mode.  
The following registered devices can be emulated using  
this mode:  
In complex mode pin 1 and pin 11 become dedicated  
inputs and use the feedback paths of pin 19 and pin 12  
respectively. Because of this feedback path usage, pin 19  
and pin 12 do not have the feedback option in this mode.  
16R8 16RP8  
16R6 16RP6  
16R4 16RP4  
Registered Configuration for  
Registered Mode(1)(2)  
Combinatorial Configuration for  
Registered Mode(1)(2)  
Notes: 1. Pin 1 controls common CLK for the registered out-  
puts. Pin 11 controls common OE for the registered  
outputs. Pin 1 and Pin 11 are permanently  
configured as CLK and OE.  
Notes: 1. Pin 1 and Pin 11 are permanently configured as CLK  
and OE.  
2. The development software configures all the archi-  
tecture control bits and checks for proper pin usage  
automatically.  
2. The development software configures all the archi-  
tecture control bits and checks for proper pin usage  
automatically.  
7

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