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ATF16V8B-7JC PDF预览

ATF16V8B-7JC

更新时间: 2024-01-20 13:35:01
品牌 Logo 应用领域
爱特美尔 - ATMEL 闪存可编程逻辑器件输入元件异步传输模式PCATM时钟
页数 文件大小 规格书
16页 658K
描述
High Performance Flash PLD

ATF16V8B-7JC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP20,.25
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.77
架构:PAL-TYPE最大时钟频率:100 MHz
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:6.5 mm湿度敏感等级:2
专用输入次数:8I/O 线路数量:8
输入次数:18输出次数:8
产品条款数:64端子数量:20
最高工作温度:70 °C最低工作温度:
组织:8 DEDICATED INPUTS, 8 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
电源:5 V可编程逻辑类型:FLASH PLD
传播延迟:7.5 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Programmable Logic Devices
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

ATF16V8B-7JC 数据手册

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Electronic Signature Word  
Input and I/O Pull-Ups  
There are 64 bits of programmable memory that are al-  
ways available to the user, even if the device is secured.  
These bits can be used for user-specific data.  
All ATF16V8B family members have internal input and I/O  
pull-up resistors. Therefore, whenever inputs or I/Os are  
not being driven externally, they will float to V . This en-  
CC  
sures that all logic array inputs are at known states.  
These are relatively weak active pull-ups that can easily  
be overdriven by TTL-compatible drivers (see input and  
I/O diagrams below).  
Programming/Erasing  
Programming/erasing is performed using standard PLD  
programmers. See CMOS PLD Programming Hardware &  
Software Support for information on software/program-  
ming.  
Input Diagram  
I/O Diagram  
Functional Logic Diagram Description  
The Logic Option and Functional Diagrams describe the  
ATF16V8B architecture. Eight configurable macrocells  
can be configured as a registered output, combinatorial  
I/O, combinatorial output, or dedicated input.  
architectural subsets can be found in each of the configu-  
ration modes described in the following pages. The user  
can download the listed subset device JEDEC program-  
ming file to the PLD programmer, and the ATF16V8B can  
be configured to act like the chosen device. Check with  
your programmer manufacturer for this capability.  
The ATF16V8B can be configured in one of three different  
modes. Each mode makes the ATF16V8B look like a dif-  
ferent device. Most PLD compilers can choose the right  
mode automatically. The user can also force the selection  
by supplying the compiler with a mode selection. The de-  
termining factors would be the usage of register versus  
combinatorial outputs and dedicated outputs versus out-  
puts with output enable control.  
Unused product terms are automatically disabled by the  
compiler to decrease power consumption. A Security  
Fuse, when programmed, protects the content of the  
ATF16V8B. Eight bytes (64 fuses) of User Signature are  
accessible to the user for purposes such as storing project  
name, part number, revision, or date. The User Signature  
is accessible regardless of the state of the Security Fuse.  
The ATF16V8B universal architecture can be pro-  
grammed to emulate many 20-pin PAL devices. These  
Compiler Mode Selection  
Registered  
P16V8R  
Complex  
Simple  
Auto Select  
P16V8  
P16V8C  
P16V8AS  
G16V8AS  
GAL16V8_C8  
“Simple”  
ABEL, Atmel-ABEL  
CUPL  
G16V8MS  
GAL16V8_R  
“Registered”  
P16V8R  
G16V8MA  
GAL16V8_C7  
“Complex”  
P16V8C  
G16V8A  
GAL16V8  
GAL16V8A  
P16V8A  
(1)  
(1)  
(1)  
LOG/iC  
OrCAD-PLD  
PLDesigner  
Tango-PLD  
P16V8C  
G16V8R  
G16V8C  
G16V8AS  
G16V8  
Note: 1. Only applicable for version 3.4 or lower.  
1-12  
ATF16V8B  

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