Datasheet > 可编程逻辑 > 可编程逻辑器件> ATF1508AS-10QU100

ATF1508AS-10QU100

更新时间： 2024-01-21 16:44:35

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程逻辑器件输入元件时钟
页数	文件大小	规格书
31页	692K
描述
Highperformance EE PLD

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技术参数
数据手册

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ATF1508AS-10QU100 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	QFP, QFP100,.7X.9
Reach Compliance Code：	compliant	风险等级：	2.04
Is Samacsys：	N	其他特性：	YES
最大时钟频率：	125 MHz	系统内可编程：	YES
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e3
JTAG BST：	YES	长度：	20 mm
湿度敏感等级：	3	专用输入次数：
I/O 线路数量：	80	宏单元数：	128
端子数量：	100	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	0 DEDICATED INPUTS, 80 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP100,.7X.9
封装形状：	RECTANGULAR	封装形式：	FLATPACK
峰值回流温度（摄氏度）：	245	电源：	3.3/5,5 V
可编程逻辑类型：	EE PLD	传播延迟：	10 ns
认证状态：	Not Qualified	座面最大高度：	3.4 mm
子类别：	Programmable Logic Devices	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	14 mm
Base Number Matches：	1

ATF1508AS-10QU100 数据手册

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Description

The ATF1508AS is a high-performance, high-density complex programmable logic device

(CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 128 logic macrocells

and up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic

PLDs. The ATF1508AS’s enhanced routing switch matrices increase usable gate count and

increase odds of successful pin-locked design modifications.

The ATF1508AS has up to 96 bi-directional I/O pins and four dedicated input pins, depending

on the type of device package selected. Each dedicated pin can also serve as a global control

signal, register clock, register reset or output enable. Each of these control signals can be

selected for use individually within each macrocell.

Each of the 128 macrocells generates a buried feedback that goes to the global bus. Each

input and I/O pin also feeds into the global bus. The switch matrix in each logic block then

selects 40 individual signals from the global bus. Each macrocell also generates a foldback

logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1508AS

allows fast, efficient generation of complex logic functions. The ATF1508AS contains eight

such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product

terms.

The ATF1508AS macrocell, shown in Figure 1, is flexible enough to support highly-complex

logic functions operating at high speed. The macrocell consists of five sections: product terms

and product term select multiplexer; OR/XOR/CASCADE logic, a flip-flop, output select and

enable, and logic array inputs.

Unused macrocells are automatically disabled by the compiler to decrease power consump-

tion. A security fuse, when programmed, protects the contents of the ATF1508AS. Two bytes

(16 bits) of User Signature are accessible to the user for purposes such as storing project

name, part number, revision or date. The User Signature is accessible regardless of the state

of the security fuse.

The ATF1508AS device is an in-system programmable (ISP) device. It uses the industry-stan-

dard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-

scan Description Language (BSDL). ISP allows the device to be programmed without remov-

ing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also

allows design modifications to be made in the field via software.

Product Terms and

Select Mux

Each ATF1508AS macrocell has five product terms. Each product term receives as its inputs

all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the five product terms as needed to

the macrocell logic gates and control signals. The PTMUX programming is determined by the

design compiler, which selects the optimum macrocell configuration.

OR/XOR/

CASCADE Logic

The ATF1508AS’s logic structure is designed to efficiently support all types of logic. Within a

single macrocell, all the product terms can be routed to the OR gate, creating a 5-input

AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be

expanded to as many as 40 product terms with a little small additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic func-

tions. One input to the XOR comes from the OR sum term. The other XOR input can be a

product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input

allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimiza-

tion of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.

ATF1508AS(L)

0784P–PLD–7/05

1 2 345 6 7...31

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