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ATF1504AS-15JC68 PDF预览

ATF1504AS-15JC68

更新时间： 2024-01-21 01:17:04
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
21页 465K
描述
High- Performance EE CPLD

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ATF1504AS-15JC68 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：LCC包装说明：PLASTIC, MS-018AE, LCC-68
针数：68Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.7
其他特性：64 MACROCELLS; IN-SYSTEM PROGRAMMABLE; JTAG BOUNDARY-SCAN TEST CIRCUITRY最大时钟频率：100 MHz
系统内可编程：YESJESD-30 代码：S-PQCC-J68
JESD-609代码：e0JTAG BST：YES
长度：24.2316 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：48
宏单元数：64端子数量：68
最高工作温度：70 °C最低工作温度：
组织：0 DEDICATED INPUTS, 48 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC68,1.0SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：225
电源：3.3/5,5 V可编程逻辑类型：EE PLD
传播延迟：15 ns认证状态：Not Qualified
座面最大高度：4.57 mm子类别：Programmable Logic Devices
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：24.2316 mm
Base Number Matches：1

ATF1504AS-15JC68 数据手册

 浏览型号ATF1504AS-15JC68的Datasheet PDF文件第3页浏览型号ATF1504AS-15JC68的Datasheet PDF文件第4页浏览型号ATF1504AS-15JC68的Datasheet PDF文件第5页浏览型号ATF1504AS-15JC68的Datasheet PDF文件第7页浏览型号ATF1504AS-15JC68的Datasheet PDF文件第8页浏览型号ATF1504AS-15JC68的Datasheet PDF文件第9页 
Figure 1. ATF1504AS Macrocell  
by mode when no logic transitions are occurring. This not  
only reduces power consumption during inactive periods,  
but also provides a proportional power savings for most  
applications running at system speeds below 50 MHz. This  
feature may be selected as a design option.  
Programmable Pin-Keeper Option for  
Inputs and I/Os  
The ATF1504AS offers the option of programming all input  
and I/O pins so that pin keeper circuits can be utilized.  
When any pin is driven high or low and then subsequently  
left floating, it will stay at that previous high or low level.  
This circuitry prevents unused input and I/O lines from  
floating to intermediate voltage levels, which cause unnec-  
essary power consumption and system noise. The keeper  
circuits eliminate the need for external pull-up resistors and  
eliminate their DC power consumption.  
I/O Diagram  
Input Diagram  
To further reduce power, each ATF1504AS macrocell has  
a Reduced Power bit feature. This feature allows individual  
macrocells to be configured for maximum power savings.  
This feature may be selected as a design option.  
All ATF1504ASs also have an optional power down mode.  
In this mode, current drops to below 10 mA. When the  
power down option is selected, either PD1 or PD2 pins (or  
both) can be used to power down the part. The power down  
option is selected in the design source file. When enabled,  
Speed/Power Management  
The ATF1504AS has several built-in speed and power  
management features. The ATF1504AS contains circuitry  
that automatically puts the device into a low power stand-  
ATF1504ASZ  
6
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