Datasheet > ATF1504AS-15JC68

ATF1504AS-15JC68

更新时间： 2024-02-26 14:02:12

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
21页	465K
描述
High- Performance EE CPLD

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技术参数
数据手册

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ATF1504AS-15JC68 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LCC	包装说明：	PLASTIC, MS-018AE, LCC-68
针数：	68	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.7
其他特性：	64 MACROCELLS; IN-SYSTEM PROGRAMMABLE; JTAG BOUNDARY-SCAN TEST CIRCUITRY	最大时钟频率：	100 MHz
系统内可编程：	YES	JESD-30 代码：	S-PQCC-J68
JESD-609代码：	e0	JTAG BST：	YES
长度：	24.2316 mm	湿度敏感等级：	3
专用输入次数：		I/O 线路数量：	48
宏单元数：	64	端子数量：	68
最高工作温度：	70 °C	最低工作温度：
组织：	0 DEDICATED INPUTS, 48 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC68,1.0SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	225
电源：	3.3/5,5 V	可编程逻辑类型：	EE PLD
传播延迟：	15 ns	认证状态：	Not Qualified
座面最大高度：	4.57 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	24.2316 mm
Base Number Matches：	1

ATF1504AS-15JC68 数据手册

ATF1504ASZ

Product Terms and Select MUX

changes state on the clock’s rising edge. When the GCK

signal is used as the clock, one of the macrocell product

terms can be selected as a clock enable. When the clock

enable function is active and the enable signal (product

term) is low, all clock edges are ignored. The flip flop’s

asynchronous reset signal (AR) can be either the Global

Clear (GCLEAR), a product term, or always off. AR can

also be a logic OR of GCLEAR with a product term. The

asynchronous preset (AP) can be a product term or always

off.

Each ATF1504AS macrocell has five product terms. Each

product term receives as its inputs all signals from both the

global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the

five product terms as needed to the macrocell logic gates

and control signals. The PTMUX programming is deter-

mined by the design compiler, which selects the optimum

macrocell configuration.

OR/XOR/CASCADE Logic

Output Select and Enable

The ATF1504AS’s logic structure is designed to efficiently

support all types of logic. Within a single macrocell, all the

product terms can be routed to the OR gate, creating a 5-

input AND/OR sum term. With the addition of the CASIN

from neighboring macrocells, this can be expanded to as

many as 40 product terms with a very small additional

delay.

The ATF1504AS macrocell output can be selected as reg-

istered or combinatorial. The buried feedback signal can be

either combinatorial or registered signal regardless of

whether the output is combinatorial or registered.

The output enable multiplexer (MOE) controls the output

enable signals. Any buffer can be permanently enabled for

simple output operation. Buffers can also be permanently

disabled to allow use of the pin as an input. In this configu-

ration all the macrocell resources are still available, includ-

ing the buried feedback, expander and CASCADE logic.

The output enable for each macrocell can be selected as

either of the two dedicated OE input pins as an I/O pin con-

figured as an input, or as an individual product term.

The macrocell’s XOR gate allows efficient implementation

of compare and arithmetic functions. One input to the XOR

comes from the OR sum term. The other XOR input can be

a product term or a fixed high or low level. For combinato-

rial outputs, the fixed level input allows polarity selection.

For registered functions, the fixed levels allow DeMorgan

minimization of product terms. The XOR gate is also used

to emulate T- and JK-type flip-flops.

Global Bus/Switch Matrix

The global bus contains all input and I/O pin signals as well

as the buried feedback signal from all 64 macrocells. The

Switch Matrix in each Logic Block receives as its inputs all

signals from the global bus. Under software control, up to

40 of these signals can be selected as inputs to the Logic

Block.

Flip Flop

The ATF1504AS’s flip flop has very flexible data and con-

trol functions. The data input can come from either the XOR

gate, from a separate product term or directly from the I/O

pin. Selecting the separate product term allows creation of

a buried registered feedback within a combinatorial output

macrocell. (This feature is automatically implemented by

the fitter software). In addition to D, T, JK and SR opera-

tion, the flip flop can also be configured as a flow-through

latch. In this mode, data passes through when the clock is

high and is latched when the clock is low.

Foldback Bus

Each macrocell also generates a foldback product term.

This signal goes to the regional bus and is available to 4

macrocells. The foldback is an inverse polarity of one of the

macrocell’s product terms. The 4 foldback terms in each

region allows generation of high fan-in sum terms (up to 9

product terms) with a small additional delay.

The clock itself can either be one of the Global CLK Signal

GCK[0 : 2] or an individual product term. The flip flop

1 2 3 456 7 8...21

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与ATF1504AS-15JC68相关器件

型号	品牌	描述	获取价格	数据表
ATF1504AS-15JC84	ATMEL	High- Performance EE CPLD	获取价格
ATF1504AS-15JI44	ATMEL	High- Performance EE CPLD	获取价格
ATF1504AS-15JI68	ATMEL	High- Performance EE CPLD	获取价格
ATF1504AS-15JI84	ATMEL	High- Performance EE CPLD	获取价格
ATF1504AS-15JJ44	ATMEL	EE PLD, 15ns, PQCC44, PLASTIC, MS-018AC, LCC-44	获取价格
ATF1504AS-15JJ68	ATMEL	EE PLD, 15ns, PQCC68, PLASTIC, MS-018AE, LCC-68	获取价格

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