Datasheet > ATF1504AS-10QI100

ATF1504AS-10QI100

更新时间： 2024-02-19 01:35:34

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
21页	465K
描述
High- Performance EE CPLD

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技术参数
数据手册

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ATF1504AS-10QI100 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	QFP, QFP100,.7X.9
针数：	100	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.87
其他特性：	64 MACROCELLS; IN-SYSTEM PROGRAMMABLE; JTAG BOUNDARY-SCAN TEST CIRCUITRY	最大时钟频率：	125 MHz
系统内可编程：	YES	JESD-30 代码：	R-PQFP-G100
JESD-609代码：	e0	JTAG BST：	YES
长度：	20 mm	湿度敏感等级：	3
专用输入次数：		I/O 线路数量：	64
宏单元数：	64	端子数量：	100
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	0 DEDICATED INPUTS, 64 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP100,.7X.9	封装形状：	RECTANGULAR
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	225
电源：	3.3/5,5 V	可编程逻辑类型：	EE PLD
传播延迟：	10 ns	认证状态：	Not Qualified
座面最大高度：	3.4 mm	子类别：	Programmable Logic Devices
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm

ATF1504AS-10QI100 数据手册

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TTL, SSI, MSI, LSI and classic PLDs. The ATF1504AS’s

enhanced routing switch matrices increase usable gate

count, and the odds of successful pin-locked design modifi-

cations.

block then selects 40 individual signals from the global bus.

Each macrocell also generates a foldback logic term, which

goes to a regional bus. Cascade logic between macrocells

in the ATF1504AS allows fast, efficient generation of com-

plex logic functions. The ATF1504AS contains four such

logic chains, each capable of creating sum term logic with a

fan in of up to 40 product terms.

The ATF1504AS has up to 68 bi-directional I/O pins and 4

dedicated input pins, depending on the type of device pack-

age selected. Each dedicated pin can also serve as a glo-

bal control signal; register clock, register reset or output

enable. Each of these control signals can be selected for

use individually within each macrocell.

The ATF1504AS macrocell shown in Figure 1, is flexible

enough to support highly complex logic functions operating

at high speed. The macrocell consists of five sections:

product terms and product term select multiplexer;

OR/XOR/CASCADE logic; a flip-flop; output select and

enable; and logic array inputs.

Each of the 64 macrocells generates a buried feedback,

which goes to the global bus. Each input and I/O pin also

feeds into the global bus. The switch matrix in each logic

Block Diagram

Unused product terms are automatically disabled by the

compiler to decrease power consumption. A Security Fuse,

when programmed, protects the contents of the

ATF1504AS. Two bytes (16-bits) of User Signature are

accessible to the user for purposes such as storing project

name, part number, revision or date. The User Signature is

accessible regardless of the state of the Security Fuse.

The ATF1504AS device is an In-System Programmable

(ISP) device. It uses the industry standard 4-pin JTAG

interface (IEEE Std. 1149.1), and is fully compliant with

JTAG’s Boundary Scan Description Language (BSDL). ISP

allows the device to be programmed without removing it

from the printed circuit board. In addition to simplifying the

manufacturing flow, ISP also allows design modifications to

be made in the field via software.

ATF1504ASZ

1 2 345 6 7...21

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与ATF1504AS-10QI100相关器件

型号	品牌	描述	获取价格	数据表
ATF1504AS-10QJ100	ATMEL	EE PLD, 10ns, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, MS-022GC-1, QFP-100	获取价格
ATF1504AS-10QL100	ATMEL	EE PLD, 10ns, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, MS-022GC-1, QFP-100	获取价格
ATF1504AS-15AC100	ATMEL	EE PLD, 15ns, 64-Cell, CMOS, PQFP100, 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-	获取价格
ATF1504AS-15AC44	ATMEL	High- Performance EE CPLD	获取价格
ATF1504AS-15AI100	ATMEL	High- Performance EE CPLD	获取价格
ATF1504AS-15AI44	ATMEL	High- Performance EE CPLD	获取价格

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