Datasheet > ATF1502ASV-20JJ44

ATF1502ASV-20JJ44

更新时间： 2024-01-24 02:18:42

品牌	Logo	应用领域
爱特美尔 - ATMEL		时钟 PC 输入元件可编程逻辑
页数	文件大小	规格书
25页	361K
描述
EE PLD, 20ns, PQCC44, PLASTIC, MS-018AC, LCC-44

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

ATF1502ASV-20JJ44 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	LPCC	包装说明：	PLASTIC, MS-018AC, LCC-44
针数：	44	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.73
最大时钟频率：	83.3 MHz	JESD-30 代码：	S-PQCC-J44
JESD-609代码：	e3	长度：	16.5862 mm
湿度敏感等级：	2	专用输入次数：
I/O 线路数量：	32	端子数量：	44
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	0 DEDICATED INPUTS, 32 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	245	可编程逻辑类型：	EE PLD
传播延迟：	20 ns	认证状态：	Not Qualified
座面最大高度：	4.572 mm	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	16.5862 mm
Base Number Matches：	1

ATF1502ASV-20JJ44 数据手册

浏览型号ATF1502ASV-20JJ44的Datasheet PDF文件第4页

浏览型号ATF1502ASV-20JJ44的Datasheet PDF文件第5页

浏览型号ATF1502ASV-20JJ44的Datasheet PDF文件第6页

浏览型号ATF1502ASV-20JJ44的Datasheet PDF文件第8页

浏览型号ATF1502ASV-20JJ44的Datasheet PDF文件第9页

ATF1502ASV

All pin transitions are ignored until the PD pin is brought low. When the power-down feature is

enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s mac-

rocell may still be used to generate buried foldback and cascade logic signals.

All power-down AC characteristic parameters are computed from external input or I/O pins, with

reduced-power bit turned on. For macrocells in reduced-power mode (reduced-power bit turned

on), the reduced-power adder, t_RPA, must be added to the AC parameters, which include the

data paths t_LAD, t_LAC, t_IC, t_ACL, t_ACHand t_SEXP

The ATF1502ASV macrocell also has an option whereby the power can be reduced on a per-

macrocell basis. By enabling this power-down option, macrocells that are not used in an applica-

tion can be turned down, thereby reducing the overall power consumption of the device.

Each output also has individual slew rate control. This may be used to reduce system noise by

slowing down outputs that do not need to operate at maximum speed. Outputs default to slow

switching, and may be specified as fast switching in the design file.

4. Power-up Reset

The ATF1502ASV is designed with a power-up reset, a feature critical for state machine initial-

ization. At a point delayed slightly from V_CCcrossing V_RST, all registers will be initialized, and the

state of each output will depend on the polarity of its buffer. However, due to the asynchronous

nature of reset and uncertainty of how V_CCactually rises in the system, the following conditions

are required:

1. The V_CCrise must be monotonic,

2. After reset occurs, all input and feedback setup times must be met before driving the

clock pin high, and,

3. The clock must remain stable during T_D.

The ATF1502ASV has two options for the hysteresis about the reset level, V_RST, Small and

Large. To ensure a robust operating environment in applications where the device is operated

near 3.0V, Atmel recommends that during the fitting process users configure the device with the

Power-up Reset hysteresis set to Large. For conversions, Atmel POF2JED users should include

the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be

properly reinitialized with the Large hysteresis option selected, the following condition is added:

4. If V_CCfalls below 2.0V, it must shut off completely before the device is turned on again.

When the Large hysteresis option is active, I_CCis reduced by several hundred microamps as

well.

5. Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF1502ASV fuse patterns.

Once programmed, fuse verify is inhibited. However, the 16-bit User Signature remains

accessible.

6. Programming

ATF1502ASV devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG proto-

col. This capability eliminates package handling normally required for programming and

facilitates rapid design iterations and field changes.

1615J–PLD–01/06

1...4 5 678 9 10...25

下载PDF

与ATF1502ASV-20JJ44相关器件

型号	品牌	描述	获取价格	数据表
ATF1502ASV-20JL44	ATMEL	EE PLD, 20ns, PQCC44, PLASTIC, MS-018AC, LCC-44	获取价格
ATF1502BE	ATMEL	Highperformance CPLD	获取价格
ATF1502BE	MICROCHIP	A high-performance, high-density, complex programmable logic device (CPLD) that uses Atmel	获取价格
ATF1502BE-5AX44	ATMEL	Highperformance CPLD	获取价格
ATF1502BE-7AU44	ATMEL	Highperformance CPLD	获取价格
ATF1502SE	ATMEL	Family Datasheet	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

ATF1502ASV-20JJ44

ATF1502ASV-20JJ44 技术参数

ATF1502ASV-20JJ44 数据手册

与ATF1502ASV-20JJ44相关器件

与ATF1502ASV-20JJ44相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ATF1502ASV-20JJ44

ATF1502ASV-20JJ44 技术参数

ATF1502ASV-20JJ44 数据手册

与ATF1502ASV-20JJ44相关器件

与ATF1502ASV-20JJ44相关文章

您还可以找

您在本页遇到什么问题？