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ATF1502AS-7JL44 PDF预览

ATF1502AS-7JL44

更新时间: 2022-12-01 19:38:44
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
26页 517K
描述
EE PLD, 7.5ns, PQCC44, PLASTIC, MS-018AC, LCC-44

ATF1502AS-7JL44 数据手册

 浏览型号ATF1502AS-7JL44的Datasheet PDF文件第3页浏览型号ATF1502AS-7JL44的Datasheet PDF文件第4页浏览型号ATF1502AS-7JL44的Datasheet PDF文件第5页浏览型号ATF1502AS-7JL44的Datasheet PDF文件第7页浏览型号ATF1502AS-7JL44的Datasheet PDF文件第8页浏览型号ATF1502AS-7JL44的Datasheet PDF文件第9页 
Input Diagram  
I/O Diagram  
Speed/Power  
Management  
The ATF1502AS has several built-in speed and power management features. The  
ATF1502AS contains circuitry that automatically puts the device into a low-power standby  
mode when no logic transitions are occurring. This not only reduces power consumption dur-  
ing inactive periods, but also provides proportional power savings for most applications  
running at system speeds below 50 MHz. This feature may be selected as a design option.  
To further reduce power, each ATF1502AS macrocell has a reduced-power bit feature. This  
feature allows individual macrocells to be configured for maximum power savings. This feature  
may be selected as a design option.  
The ATF1502AS also has an optional power-down mode. In this mode, current drops to below  
10 mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be  
used to power down the part. The power-down option is selected in the design source file.  
When enabled, the device goes into power-down when either PD1 or PD2 is high. In the  
power-down mode, all internal logic signals are latched and held, as are any enabled outputs.  
6
ATF1502AS(L)  
0995K–PLD–6/05  

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